In this role you will be familiar with cutting edge power management techniques including power management ICs control schemes, Chip power state transitions, SoC boot process and HW security solutions. You will define uArch spec, implement HW including RTL and UPF coding, synthesize the digital design to the latest process nodes and participate in the implementation process.
Your responsibilities in this role likely to include:
Micro-architecture definitions at the unit level.
RTL coding, block level simulations and synthesis.
Work closely with verification team on block/top level to ensure timely delivery of quality designs.
Work closely with physical design team to optimize the design and to meet the targets set for a certain unit (area, timing, and power).
The position is relevant to all our sites: HRZ, Haifa, JRZ.
Imagine what you could do here. In our company, new ideas have a way of becoming extraordinary products very quickly.
Do you want to bring passion and dedication to your job? There's no telling what you could accomplish in our company. Do you want to join us to help deliver the next groundbreaking our products?
The SoC design team is looking for an experienced engineer to develop our compute SoCs power management system. Role expectations include working with partner Design teams, Physical design, verification, Platform Architecture and Software teams to define the power system micro architecture, implement the required HW and integrate it to a complex multi chip system.
Requirements: Minimum Qualifications:
3+ years of experience in digital design (preferably in SoC).
Familiar with advanced design practices (clock/voltage domain crossing, low power design and DFT) - Advantage.
Familiar with various chip development tools (e.g. lint, synthesis, STA).
Familiar with verification methodologies.
Strong Verilog/System Verilog skills.
Experienced with scripting using common languages (e.g. Python, Perl, TCL).
Preferred Qualifications:
BS.c/ MS.c in EE/ CE.
This position is open to all candidates.
