לוח משרות דרושים Backend Engineer משרה מלאה

we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up.
If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us.

As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the worlds largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring our silicon meets the extreme performance, power, and area (PPA) targets required for AI scale.

Key Responsibilities


Execute SoC Top-level physical design and actively drive full-chip convergence
Perform Top-Level physical implementation, including floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, and Timing/Physical signoff
Work closely with the Architecture, Design, DFT, and Product teams to achieve optimal Power, Performance, and Area (PPA). This involves participating in feasibility studies for new architectures and optimizing runs to ensure the best Quality of Results (QoR)
Resolve complex signal integrity, thermal, and power challenges inherent in high-speed connectivity silicon
Collaborate closely with the Package team on Bump-map-to-Ballout design, taking all signal integrity aspects into consideration

we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team.


Key Responsibilities


Develop and maintain automated flows for Synthesis, Place & Route (P&R), and Floor-planning to ensure seamless design transitions
Implement and manage robust environments for Static Timing Analysis (STA), Power Analysis, and Physical Verification (DRC/LVS/ERC)
Write and maintain custom plug-ins and scripts (Tcl/Python) to extend vendor tool capabilities, tailoring them to specific process node constraints
Build automated "dashboards" and feedback loops to track and improve Power, Performance, and Area (PPA) metrics across design iterations
Own the design database structure and version control to ensure team alignment and data integrity
Collaborate directly with EDA vendors (Synopsys, Cadence, Siemens/Mentor) to troubleshoot flow issues and analyze tool results
Provide technical support to the broader PD team, helping them optimize individual blocks for power, performance, and timing

Were looking for a Senior Backend Engineer to help us evolve and scale our real-time incoming infrastructure. Youll solve high-throughput, low-latency challenges and craft APIs used by some of the largest mobile apps in the world.

What youll do
Design, build, and own real-time engagement services and APIs that are fast, reliable, and scalable.
Evaluating architectural trade-offs (e.g., consistency vs. availability) in a distributed environment.
Tackle complex problems in real-time, high-throughput systems using modern cloud-native tooling such as CDNs, WAF, Web Handlers, and Kafka
Lead API design and implementation across systems - with a strong focus on security, scale, performance, and reliability
Identify and resolve systemic bottlenecks that span multiple services or cloud regions.
Collaborate with Product Managers and Engineers to shape product direction and deliver customer value
Contribute to engineering excellence via code reviews, mentoring, and technical leadership
Continuously evaluate and integrate new technologies to keep our stack modern and efficient

we are looking for a talented Senior Software Engineer
The team is responsible for processing structure and unstructured medical data from multiple external sources while building and maintaining an internal serving platform. Our key challenges include operating at scale, integrating with diverse external interfaces, and ensuring the data is served in a consistent and reliable manner.
Responsibilities:
Lead development processes from ideation to production
Collaborate with product, medical, and software teams across the organization.
Own the design and evolution of the data ingestion and serving platform.
Mentor and guide junior and mid-level engineers.
Define best practices for system reliability, scalability, and observability.
Lead technical decisions around distributed systems, APIs, and integrations.
Build a customer-centric product with a deep understanding of the complex healthcare industry.

As a Backend developer in the team, you will be a part of delivering new features, as well as building core components with performance in mind. This role is ideal for a highly skilled developer who is passionate about building scalable and reliable infrastructure and thrives in a fast-paced, innovative environment.
What youʼll do:
Implement and deliver new features according to productsʼ requirements
Implement enhancement features and build the infrastructure to support the scale of the product.
Participate in design discussions and code reviews
Develop unit and integration tests
Assist in solving real-time customer issues.

We are seeking a Senior Backend Engineer with proven experience in large-scale systems and a deep understanding of performance and scalability to drive the evolution of our rapidly growing application.
In this position, you will be part of delivering complex features while building the infrastructure required to support our product's enterprise-level growth. You will be involved in the entire lifecycle, from product requirements and technical design to implementation, for a complex system used by major global financial carriers.
What you will do:
Implement and deliver new features based on product requirements.
Implement enhancement infrastructure to support the scale of the product.
Deliver high-quality features, including AI-driven functionalities that enhance decision-making and user experience.
Participate in design discussions and conduct code reviews.
Develop unit and integration tests.
Assist in resolving real-time customer issues.
Actively share knowledge with other team members to tackle technical challenges.

You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.

Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

we are looking for an AI Platform Engineer to revolutionize engineering productivity and drive AI-powered innovation across the organization. This role is part of our Platform Engineering initiative, focused on enabling engineers and product teams with cutting-edge AI tools, intelligent automation, and scalable AI platforms.
If youre an innovator at heart, passionate about applying AI to solve complex engineering problems, and thrive in an environment that values experimentation, ownership, and entrepreneurship-this role is for you.
Responsibilities
Develop and integrate AI-powered solutions that enhance engineering productivity, automate workflows, and improve developer efficiency across the organization.
Evaluate, prototype, and implement state-of-the-art AI platforms using latest models and frameworks (e.g., ChatGPT, Claude, Gemini, LangGraph, Librechat, AWS Agentcore Bedrock) to address engineering and operational challenges.
Design, build, and maintain AI-driven internal platforms, including knowledge management systems, AI-enhanced coding assistants, intelligent automation tools, and AI-powered chatbots.
Collaborate closely with engineering, DevOps, and product teams to embed AI capabilities into everyday development workflows.
Lead Proof-of-Concept (PoC) initiatives, experimenting with LLMs, generative AI, and automation frameworks to deliver tangible business impact.
Research emerging AI trends, tools, and models, and translate them into practical, production-ready solutions.
Build and operate scalable AI infrastructure that integrates with cloud environments and existing engineering toolchains.
Promote a culture of innovation by empowering teams to adopt AI-driven solutions and sharing knowledge and outcomes across the organization.

you will be developing physical design, sta, logic eq, power integrity flows and methodologies for implementation of networking chips and socs.
work closely with block owners, full chip sta engineers to assure high quality and timely convergence.
come up with unique and creative solutions to the state of the art physical design problems that are needed for our chips.
additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, ir-drop, em and back-end verification across multiple projects.

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part in flows development.

which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.