The group specializing in ASIC Development from Architecture to Post Silicon through RTL Design and UVM Verification.
We are looking for Physical Design / backend Engineer to join our team.
Requirements: B.Sc./M.Sc. in Electrical Engineering
4 years of experience with RTL2GDS P R (Place and Route) flow (ICC2/Innovus) with STA closure
4 years of experience in Full Physical verification flow (DRC/LVS/DFM) with ICV/CALIBRE
4 years of experience in Developing backend flow and methodologies with Cadence or Synopsys tools.
Checking and performing IR-drop, ESD Electromigration analysis is an advantage
Script writing skills with TCL/ Python /sed/awk
Basic knowledge in Structural Design (Synthesis, Timing closure, Formal Equivalence Check) an advantage
Low Power Design including Power intent (UPF) definition verification an advantage.
Experience in RTL blocks design (Verilog/VHDL) an advantage.
Personal Profile:
Ability to work in an independent mode.
Excellent communication skills
Team player
Multitasking, self-motivated, and problem solver
Excel
This position is open to all candidates.
