לוח משרות דרושים מהנדס פיזיקה בחיפה וסביבתה

You'll be joining our Silicon One Signal & power Integrity team, which is at the center of the silicon development at Cisco. Our SIPI engineers deal with all system development aspects and deliver detailed specifications to other development team. As SIPI engineer youll be required to design and analyze high speed analog/digital signals for networking products, with emphasis on high speed signal and power analysis of ASIC, Package and PCB. Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenges of ultra-high data rate and cutting-edge technology. We use the latest silicon technologies and processes to build largest scale and most complex devices at the edge of feasibility.

as a quality and reliability (q&r) engineer, you will lead the qualification and long-term reliability of advanced system -on-chip ( SOC ) and RF semiconductor products for automotive applications. youll work across digital and RF domains to ensure robust performance and compliance with industry standards.
what will your job look like:
define and manage quality and reliability specifications, simulations, and qualification plans for SOC and RF die and package.
plan and execute automotive-grade qualifications per standards such as aec-q100, jedec jesd22, and iatf 16949.
design and implement die-level and package-level stress tests.
select and prepare electrical, environmental, and mechanical TEST platforms for reliability testing.
define requirements for pre-si q&r (e.g. esd, lu, em, ir drop), design-for- TEST (dft), electrical characterization, and post-si q&r testing of digital, mixed-signal and RF socs.
collaborate extensively with internal design teams, external subcontractors, and outsourcing partners (osats).
lead failure analysis, reliability modeling, and corrective action processes (e.g., 8d, fmea, fmeda).
document and certify automotive standards compliance, including ppap/apqp deliverables.

we are seeking a skilled failure analysis (fa) engineer with expertise in x-ray inspection techniques to join our av platform team. the ideal candidate will specialize in using advanced x-ray imaging and other analysis methods to investigate product failures, identify root causes, and provide actionable insights to improve product quality and reliability what will your job look like?
perform detailed failure analysis using x-ray imaging systems and related diagnostic tools to inspect electronic components, assemblies, and materials.
interpret and analyze x-ray images to detect structural anomalies, defects, voids, cracks, delamination, and other failure mechanisms.
develop and optimize x-ray inspection procedures and protocols for failure analysis and quality control.
prepare TEST specimens: cutting, mounting, grinding, polishing and chemical etching
collaborate with product engineering, Quality Assurance, and manufacturing teams to support product development, troubleshooting, and continuous improvement efforts.
prepare detailed technical reports documenting findings, root cause analyses, and recommended corrective actions.
support reliability testing and failure mode analysis for new and existing products.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

The Test & Product team is responsible for keeping a target of a very aggressive cost limit of the production testing (wafer sort) while performing comprehensive testing of all the units functionalities. This involves:
Development of the tests using the Teradyne UF tester.
Development of unique and advanced test HW.
Monitoring and analyses the production data.
FA (Failure Analysis) when issues are discovered.
Innovative DFT (design for testability) with the design team.

Responsibilities:
Development of wafer sort test programs through a close relationship with the system team.
Development of the future products DFT and DFM through close collaboration with the design team.
Improvement of the production data analysis and reports through close relationships with the cloud and data teams.
Working with the external abroad test houses.
Decision-making based on massive data analysis (pass criteria, improvements of the tests, identification of failures).
Integrate new and innovative testing methods for a new technology sector.
Specify and work with external vendors for the tester HW (Probe-card and Load-board).
Specify and work with external vendors for the HTOL HW, test program.