We are seeking a highly skilled and experienced Principal Digital IC Verification Engineer to join our dynamic team. The Principal Digital IC Verification Engineer will play a crucial role in ensuring the quality and reliability of our ASIC based Wireless and Wired communication chips by designing, developing, and executing comprehensive verification plans. The ideal candidate will have a strong background in ASIC verification methodologies and will possess excellent problem-solving skills. In this role, you will focus on the followings:
Block Level verification of complex Design modules
Cluster/system level testing including: Simulating system level scenarios, Performance evaluation, Software debug
Writing verification environments from scratch
Integrating block level environments into cluster/system environments
Define and implement architectural changes for the verification infrastructure
Requirements: Extensive knowledge in System Verilog UVM verification methodologies (or Specman eUVM)
Experience in writing complex block level verification environments including: Definition of testplans, Environment architecture and coding, Debug and coverage closure
Experience in system level testing
BS in Electrical Engineering or related + 8 years of experience, or MS + 6 years of experience, or Ph.D. + 3 years of experience
Preferred Qualifications:
Experience with verification of complex digital designs, including processors, interfaces, and DSP blocks
Familiarity with formal verification techniques and tools
Knowledge of hardware description languages such as Verilog
Experience with emulation and/or FPGA prototyping
Knowledge in scripting Languages such as Python
This position is open to all candidates.
