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Review micro-architecture specifications

Supervise verification team members and provide professional guidance

Implement Verification environment UVM based

Collaborate with Design engineers to resolve bugs and achieve coverage closure

Work with the firmware/Lab teams to verify chip flows

Perform debug, root-cause analysis, and post-silicon validation in the lab

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity

Develop advanced verification environments using SystemVerilog and UVM
Write, run, and debug testbenches to ensure complete functional coverage
Drive pre-silicon and in-lab debug activities to resolve complex issues
Collaborate with RTL, architecture, and physical design teams to achieve design closure
Support methodology development, scripting, and automation to enhance productivity
Contribute to the success, powering the next generation of Internet infrastructure

In this role, you will be part of the Silicon One Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.

* Handle all chip validation aspects, including:
* Building validation plans.
* Deloping ASIC software test infrastructure.
* Writing tests in Python/C++ over device SDK.
* Executing tests and analyzing results.

Lead the functional sign-off for complex FPGA designs by architecting scalable, reusable UVM-based verification environments.
You will build the essential infrastructure that empowers FPGA designers to efficiently and accurately verify their own modules.

Key Responsibilities:
* Architecture: Build and maintain advanced simulation environments from scratch using UVM and SystemVerilog.
* Strategy & Coverage: Develop comprehensive verification plans to drive the team toward 100% functional and code coverage closure.
* CI/CD & Automation: Architect robust automated regression testing environments and integrate them into CI/CD pipelines (e.g., Jenkins).
* Tool Expertise: Serve as the internal authority for EDA tools (like Questa) and manage high-performance simulations.
* Debugging: Perform deep root-cause analysis on complex failing tests and hardware logic.

our companys innovative processors are designed into the advanced cellular systems of most tear-1 carriers .
We are looking for an experienced and creative Verification Engineer to join our Processor Verification Team.
In this role, you will be responsible for verifying the core units of our next-generation processors. You will work closely with the architecture and design teams to ensure functional correctness through advanced verification methodologies, taking ownership of verification environments from planning to coverage closure.

we are looking for an experienced SW engineer with desire and ability to contribute and lead cutting edge network management system of most powerful super-computers in the world. our team is growing, and we are looking for hardworking and self-motivated engineers to lead building of advanced, high scale sdn management solutions. you will be part of a dynamic team, working with amazing people. this crucial role will give you a rare opportunity to craft and deliver a new class of data center nms product line.
what you'll be doing:
the team develops infrastructure for monitoring and gathering telemetry from production environments, running on the worlds largest supercomputers and datacenters.
the work environment is dynamic and challenging; we are innovating and inventing software products at the forefront of technology in terms of performance, scalability, and features.
our team works closely with other engineering teams to co-design new features and software apis

looking for a best-in-class engineer for an exciting role as a pre-silicone technical leader capable of leading complicated pre-si programs while fine-tuning existing and defining new methodology processes. be a key player in the networking hardware and software development path and contribute to the latest breakthroughs in high performance networking appliances. lead the pre-si technical programs from initial mrd presentations through "all hands" bring up events towards final customer samples release. pave the way to improved methodology and streamline processes. we develop sw and fw pre-silicone features, solutions and tools for next-generation asics, and orchestrate the pre-silicone process and asics bring-up events.
what youll be doing:
leading a multi-functional cross org team, responsible for ensuring critical software and firmware is ready to support the bringup of new switch asics
driving technical issue resolution to enable single day silicon bring up on multiple sw/hw layer while meeting aggressive product schedules.
drive, improve and introduce in-team and cross-team processes to guarantee high quality pre-silicon execution.
interface and drive pre-silicon issues across multi-functional teams: product management, architecture, software design and verification, system hardware and software, system and ic product engineering teams and others. drive technical sessions with multi-functional teams to track & follow-up on issues, progress and escalations.
focused issue reporting, bug tracking, and communication of pre-si technical program risks & status.

We are looking for a Senior Verification Engineer to be a significant part in developing a complex and innovative SoC chip in a start-up company.

Taking full ownership of entire domain, defining the verification strategy, writing, and executing verification plan in system Verilog UVM.

Joining our growing and versatile team, youll contribute to the development and verification of groundbreaking ML and Neural Network hardware. Collaborating with experts across global design centers, youll drive impactful projects and help deliver Arms next-generation IP using the most sophisticated tools and methodologies.

As a verification engineer, you will make a difference by influencing the verification strategy and methodology, taking ownership of complex work packages and driving them to success.

Required Skills and Experience:

Meticulous attention to detail, ensuring high-quality verification that minimizes bug escapes.
Shown experience in block-level verification using UVM or similar methodologies.
Strong knowledge of coverage driven verification for complex designs.
Proficient in specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches.
Skilled in planning verification tasks and producing realistic effort and time estimates.