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we are looking for a senior software engineer to join our team developing software solutions to control nvidia hw in Python on Linux for various internal engineering groups, including chip designers, algorithm engineers, phy characterization engineers, optics engineers, and other r&d teams. our work includes building and maintaining a framework, as well as developing gui tools that support complex engineering workflows. this role combines advanced software engineering with a hardware-oriented perspective - the ideal candidate should have both the interest and background in areas such as hardware, Linux systems, and low-level drivers.
collaborate with the development team to improve existing framework and tools, suggest creative solutions, and develop new projects.
in our group, software engineers are responsible for the full lifecycle of solutions - from defining requirements and designing architectures to implementation, integration, and delivery. this approach allows every team member to grow professionally, develop a broad skills, and unlock their full potential.
what youll be doing:
design, develop, and maintain Python -based software solutions (framework, internal tools, gui applications with pyqt).
collaborate with internal customers - including chip designers, algorithm engineers, optics engineers, phy characterization engineers, and other r&d teams - to understand requirements and translate them into robust solutions.
take full ownership of projects: define the solution, design the architecture, implement, integrate, and support production-ready tools.
extend existing framework and tools, while also designing and implementing new ones from scratch.
work within Linux environments, integrating software with hardware interfaces, drivers, and engineering workflows.
apply oop principles and design patterns to build scalable, maintainable software architectures.

we are looking for best-in-class physical design engineers to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
what you'll be doing:
physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
be exposed and work on a variety of challenging designs (including high cell count and hs blocks). resolving complex timing and congestion problems.
daily work involves all aspects of physical design chip development (rtl2gds) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
taking part inflows development.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.

Required Senior Board Designer
Role Summary:
Serve as a key contributor within a hardware design team developing advanced ultrasound systems.
Lead and execute high‑quality PCB design with a focus on performance, reliability, manufacturability, and cost.
Collaborate with internal engineering groups and external partners to develop complex system modules.
Provide ongoing support, maintenance, and continuous improvement for legacy hardware platforms.
Job Responsibilities:
Drive the design and development of digital and analog circuitry across the full product lifecycle - from concept and prototyping through mass production.
Perform circuit analysis, simulations, and signal integrity verification for both analog and high‑speed digital designs.
Apply critical thinking and problem‑solving skills to identify issues, propose solutions, and communicate findings clearly.
Utilize Cadence/OrCAD tools for schematic capture and PCB layout.
Work effectively with cross‑functional teams, including mechanical, firmware, manufacturing, and external ODM partners.
Lead electrical design activities with external teams, ensuring technical alignment and high‑quality delivery of system sub‑modules.
Produce clear, thorough engineering documentation and communicate design decisions effectively.

we're the driving team behind groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhsic hardware description language (vhdl)), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

The wireless system engineer is a key position in a multidisciplinary R&D organization and acts as a technical lead for all matters related to wireless system design in new and existing products.
In this role you will be part of a dynamic team responsible for defining the architecture of a product, targeted to the Wireless Backhaul Market for 5G deployments.
Understand and analyze customer needs and market trends.
Define hardware, firmware and software requirements while supporting other R&D and Engineering teams, during all project phases.
Support field trials, customer challenges and production processes.

we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

we are looking for a creative, independent product engineer to join our company networking business unit. for over two decades, our networking has continuously reinvented itself, delivering industry leading high speed interconnect products. our solutions set the standard for performance, scalability, and innovation enabling true end to end high speed ethernet and infiniband solutions.
as we continue to grow, we are seeking exceptional engineers to help drive the next wave of technological advancement. in this role, you will take a leading position in the interconnect cluster performance domain. you will work closely with global technical teams to gain deep architectural insight, investigate customer complaints, and drive product excellence. if you are passionate about building high-quality products that make a real-world impact, we want to hear from you.
what youll be doing:
maintain high-quality product deliveries through in depth Big Data analysis and failure analysis
improve product performance by collaborating with process, mechanical, hardware, and thermal teams
lead high impact task forces and cross functional working groups
help design and enhance product TEST plans to ensure high customer satisfaction
manage failure analysis for both field and lab issues
collaborate closely with customer support, marketing, engineering, quality, and reliability teams

As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal, mechanical, and cost targets, enabling products to operate reliably in the worlds most demanding AI and cloud environments.

Key Responsibilities


Execute end-to-end IC package design, from early feasibility and detailed design through to qualification and high-volume manufacturing
Implement package architecture and utilize advanced technologies (organic substrates, advanced laminate, interposers, multi-die/chiplet packaging, CoWoS - 2.5D/3D integration)
Drive signal integrity (SI), power integrity (PI), and thermal considerations at the package level for high-speed, high-power devices
Perform package layout, substrate routing, bump/ball maps, stack-ups, materials selection, and apply mechanical constraints
Collaborate closely with silicon design, SerDes, system, SI/PI, and reliability teams to optimize overall product performance
Interface directly with OSATs, substrate vendors, and manufacturing partners to ensure design-for-manufacturability (DFM), yield, and cost targets are met
Conduct package-related risk assessments, failure analysis, and corrective actions during bring-up and production ramp
Support NPI, qualification, and product sustainment activities, including vendor technical reviews

looking for an experienced electronics/ system Engineer to serve as a technical project leader (tpl), join our organization, and be a part of the system product engineering organization. the team delivers brand new, high-quality products to nvidia's customers, applying the following: development and deployment of automatic testers for nvidias network business units (computing network adapters and high-speed switch systems) including hardware, software, and mechanics; coordinating and leading all aspects of the analysis of manufacturing data to identify and mitigate quality issues using advanced data analysis techniques such as Machine Learning, statistical tools, and ai; leading smooth production and capacity enlargement and failure analysis of return material from customers to understand the reason for failures ;validating TEST performance and stability using QA (v&v - validation and verification) methods; the tpl leads projects from requirement until end of life; engineering manager for spe projects and technical authority across spe teams
what youll be doing:
building integration plans, communicating status and priority among the teams (in/outside of spe), assessing risks and developing mitigation plans
leading the project lifecycle in the spe group, which starts at the requirements stage, through chip design and fw stages till spe mp, including quality and yields improvement plans
responsible for bugs management prioritization and tracking and relevant knowledge transfer to the spe group
working closely with development teams for environment improvements, such as automation, and driving mitigations to reduce risks
collaborating with pm for schedule tracking and modifications
evaluating new technologies and testing capabilities for improvement
working with the testing architecture team (dft) to assure testing setups and coverage are met
engaging with a variety of teams: r&d, hw and sw, chip design, operations, thermal, signal integrity, fw and sw, layout, and more, report project status for high level management

Your role:

Design, implement, integrate, and test a (sub)system, component, or module in high quality, according to requirements and on time.
Comply and align with software development professionalism standards within the team (processes and methodologies, quality of requirements, design, coding, and testing).
Carry out complex development and prototyping tasks.
Understand market needs and translate them into implementation requirements while considering the overall solution.
Work on multiple projects, including new product life cycle development as well as maintenance of already released products.
Promote domain knowledge, innovative thinking, and customer understanding.
Promote trust and openness, and leverage external capabilities locally and globally.
A career at Philips comes with all sorts of wonderful benefits. Be sure to speak to your recruiter about benefits in your region.

In this role, you will design complex boards from the requirements stage to bring up, support, and production.
Your tasks will include: requirements collection, design specifications, circuit design, component selection, schematic capture, circuit simulations, accompany layout with PCB designer, documentation, acceptance test specification, bring-up, debugging in the lab, and user support.
A significant part of the job will require proactive interaction with peers in Israel and in California.

we are looking for a creative and independent software engineer for tools, infrastructure, and workflows development for the ic TEST and product engineering group in our networking business unit. our company networking business unit has continuously reinvented itself over two decades. our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another and today we are known as the go-to place for end-to-end high-speed ethernet and infiniband solutions.
we're looking to grow our company and build our teams with smart people who can join us at the cutting-edge technology. we are seeking a creative visionary who will thrive in our innovative environment, who will help move network silicon ics products (switch, nic, smartnic) from design to mass production. you will collaborate with TEST engineers, TEST house, design, it and many other professionals in the organization for the development of TEST infrastructure for speeding time to market and enabling next generation TEST capabilities, characterization and data analysis. at our company , we foster a collaborative and inclusive culture where your ideas can make an immediate impact. if you are passionate about enabling of the highest quality network products in the market, we want to hear from you!
what you'll be doing:
design, develop, and maintain runtime infrastructure libraries for ate systems.
enhance TEST program architecture and infrastructure for next-generation products.
collaborate with contract manufacturers to enable new TEST capabilities.
work cross-functionally across design, product, and operations teams to improve quality and time-to-market.

seeking a passionate senior software engineer to join our Embedded processing software sdk development team. we are seeking hardworking and experienced engineers to contribute to the development of advanced networking and Embedded processing software. you will be part of a team developing next-generation Embedded processor sw, working closely with other sw r&d teams and sw architects.
what you will be doing:
design and develop advanced features for our world-class Embedded processing
write clean, efficient, and maintainable code using advanced ai-based tools
collaborate with team members, sw r&d, architects, compiler team, and fw

Key Responsibilities:
Assemble, build and install test setups and development platforms.
Utilize debug tools and cutting-edge lab equipment to support sophisticated, multidisciplinary debug activities.
Perform mechanical reworks.
Prepare various parts for tests and internal end-to-end system integration (parts/PCBs, cables, etc.).
Assembly of electro-mechanical parts.
Soldering wires and components.
Will to learn unique processes, working methods and tools.
Use of basic hand tools , such as a hammer, tape measure, plaiers, wrenches, screwdrivers, wire stripers and more.
Basic DIY skills.