We are is looking for a talented Code Generation and Optimization Expert. We are looking for a self- , independent engineer to join the team that builds the software infrastructure for accelerating the system in large scale compute environments like data centers and HPC using new CPU core technology. Working on the cutting edge and future ready systems. We work in a development culture that is diverse, flexible and challenging. For persons looking to make an impact and influence the future of computing with personal growth options.
The CodeGen team is developing core components in the automated optimization process that adapts our unique hardware architecture to run any HPC & AI applications, with little to no code modifications required. By using iterative rounds of telemetry and optimization, our compiler is able to intelligently adapt our accelerator into a workload-specific ASIC, at runtime.
We are seeking a talented Code Generation and Optimization Expert to join our bleeding-edge CodeGen team in Israel. In this high-visibility, hands-on role, you will play a pivotal part in building NextSilicons next-generation runtime compiler.
Responsibilities
Design and maintain the distributed and heterogeneous executable that is generated by our compiler stack.
Using the MLIR framework, transform high level compiler outputs into hardware-specific binary images, memory mappings, execution parameters, resource allocation, region grouping, and cross-domain coordination for distributed systems.
Design and maintain the API layer (libRT.a) connecting compiler-generated code with runtime services, ensuring seamless integration across different execution domains.
Collaborate closely with hardware, architecture, verification and other compiler teams to align software with hardware requirements and behavior.
Requirements: Education: B.Sc. or higher in Computer Science, Computer Engineering; or equivalent experience.
Strong background in modern C++ (C++11 and newer) and system-level software development.
5+ years software engineering experience in large/complex projects.
Strong data structure intuition, graph operations, and algorithm design.
Comfortable working in hardware-aware environments, even if not directly writing low-level drivers or firmware.
Experience in chip development flows, hardware simulation, system modeling, embedded/real-time systems development, and data structure design, including complex serialization formats: an advantage.
Proficiency with hardware-aware deployment and model behavior in generative AI mechanics: an advantage.
Familiarity with compiler engineering concepts (IR, optimization techniques, dataflow analysis): an advantage.
This position is open to all candidates.