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Required Design Team Manager, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required RTL Design Technical Lead, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Staff Design Engineer, Networking, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

Annapurna Labs, a fabless semiconductor company founded by industry veterans, operates as part of us.
We develop leading-edge semiconductor products that power Amazon's cloud infrastructure.
As a startup-like organization within us, we create technologies that drive the world's largest cloud provider. Our engineers work with cutting-edge technologies to innovate and shape the future of cloud computing. At Annapurna Labs, you'll experience a fast-paced environment that offers continuous learning opportunities and the chance to develop next-generation platforms.

Required Junior SoC DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Haifa, Israel; Tel Aviv, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Testing (DFT) Engineer, you will be responsible for defining, implementing and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for a CPU. You will design, insert and verify the DFT logic.You will prepare for post silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality and enhancing yield.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our platforms, we make our product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

We are seeking a CAD Engineer to join the Silicon One Physical Design team.
Meet the Team:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As part of our team, youll contribute to the development of our next-generation network devices. Our team operates in a startup-like environment within a stable and leading corporation.
Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof.
We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of our future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility.
We are a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine!
Your Impact:
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be leveraging your backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.

We are seeking a HW Board Design Engineer.
Meet the Team:
Youll collaborate with top industry engineers within the fast-growing Silicon One group worldwide.
You will be part of a team driving our groundbreaking next-generation network devices. Our team operates in a startup-like atmosphere within a global, leading corporation.
Our design center is unique, hosting all silicon hardware and software development fields under one roof. Our Networking Chips deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility. They are strategically placed in critical AI infrastructure, powering next-generation network devices and supporting advanced AI workloads. They deliver high speed without compromising programmability, buffering, power efficiency, scale, or feature flexibility.
Your Impact:
Spearhead innovative silicon architecture for AI infrastructure, guiding board design from concept through to mass production.
Act as the technical decision-maker for the project and collaborate with cross-functional teams in mechanics, thermal, PCB layout, and software/RTL.
Define product specifications, develop electrical schematics, and guide component selection.
Conduct hands-on testing in a lab environment and drive the PCB bring-up, characterization, and debugging stages.

We are looking for
For our Aerospace Division site in Haifa, we are looking for an Architect with extensive experience in signal processing and 3D imaging to join a multidisciplinary systems and algorithms group developing an innovative and groundbreaking Imaging Radar solution for airborne platforms
This is a unique opportunity to be part of the development of advanced defense technologies, work on complex multidisciplinary systems, and contribute to cutting-edge radar imaging capabilities with real operational impact
In this role you will
Develop and implement advanced radar signal processing algorithms and 3D image reconstruction capabilities
Define, execute, and analyze laboratory, field, and flight experiments
Analyze data and derive conclusions for implementation within the product
Develop and operate dedicated simulation tools for algorithmic research
Integrate complex systems
Work within a multidisciplinary team environment
Collaborate closely with technical management, mechanics, software, hardware, operational research, system engineering, and product management teams.

We are looking for an Embedded Software Engineer for performance verification and profiling.
You will join the Virtual Platforms and Performance Verification team in the EyeQ Platform Group (EPG), working on current and next-generation ADAS/AV systems.
Virtual platforms, performance models, and profiling tools are core components of the EPG infrastructure. These tools are used during the pre-silicon phase for hardware architecture optimization and software development, and in the post-silicon phase for software performance optimization.
What will your job look like:
Performance verification of EyeQ SoC designs
Development of hardware virtual platforms
Running hardware benchmarks and correlating virtual platform results with silicon measurements
Development of tracing and profiling tools for CPU performance analysis and optimization
Close collaboration with hardware architects and software, OS, and algorithm teams.

We are looking for a talented Architect to join us. As a Data Architect, you will be the organizational point of contact for all things related to data persistence and architecture. You will work closely with engineering teams across the Product, Platform, and Data groups to design, govern, and evolve our data models, databases, and data-related systems. Your goal will be to ensure scalability, reliability, security, and efficiency for all data storage and retrieval across the organization.

A few of the things you will do:

Be the primary point of contact and subject matter expert for data persistence across the entire engineering organization.

Define and govern the data architecture strategy, standards, and best practices for relational, NoSQL, and data warehouse systems.

Partner with engineering teams from product, platform, and data groups to design and implement scalable and robust data models for new and existing services.

Lead the design and optimization of the organizations data flows. You will help to ensure that data moves efficiently, consistently, and with high quality across all systems and domains.

Evaluate and recommend new technologies and data solutions to meet evolving business needs.

Drive initiatives to improve data quality, consistency, and integrity across all production systems, from ideation to hands-on execution.

Establish, maintain, and communicate documentation for all data models and architectural decisions.

we are looking for a AI Architect.
Responsibilities:
1. AI Architecture & Technical Leadership
Guide AI architectural direction across Navinas platform, focusing on system design, model lifecycle, and integration of AI components into product workflows.
Act as a senior technical reviewer and thought partner for complex or cross-team AI design decisions.
Provide technical oversight on areas such as exploring new models/technologies/opportunities for the company
Surface architectural risks, tradeoffs, and long-term implications, including cost, security and compliance aspects and clearly advise the VP of AI when certain technical directions should not be pursued.
This role influences judgment, clarity, and experience, not through blocking authority.
2. Hands-on Applied Innovation (Core Pillar | ~50%)
Spend at least 50% of time hands-on, building:
End-to-end AI prototypes
Technical demos and proofs of concept
Exploratory implementations of new AI capabilities
Drive applied innovation that:
De-risks new technologies
Demonstrates feasibility and impact
Informs product direction and business opportunities
Build fast, concrete examples that teams can learn from and extend.
Transition successful prototypes to team ownership for further development and scaling.
This role is expected to lead AI innovation by doing, while working closely with product, medical and engineering
3. Best Practices & Technical Enablement
Define and promote best practices for applied AI development, including:
Rapid prototyping and vibe coding.
Agent design, orchestration, and evaluation patterns
Experimentation, benchmarking, and validation workflows
Help teams align on shared technical patterns, tools, and standards.
Identify opportunities to consolidate duplicated efforts and improve cross-team coherence.
Lead technical deep dives, architecture discussions, and design reviews.
4. AI Compliance & Regulatory Enablement (Technical Scope)
Ensure Navinas AI development practices align with applicable AI regulations for a software product handling sensitive medical data.
Define and guide AI-specific compliance practices, including data usage, transparency, evaluation, and documentation expectations.
Support and contribute to AI-related compliance and regulatory documentation, in close collaboration with Legal, Security, and Medical Research teams.
Serve as a technical point of reference for AI compliance questions.

We're looking for a Backend Architect to be the technical authority across our engineering teams. This is a hands-on leadership role for someone who loves diving deep into complex systems while keeping the big picture in mind.

You'll work closely with three cross-functional development teams - shaping the backend architecture, driving engineering standards, and making sure we're building for scale, reliability, and long-term maintainability.

Responsibilities
Own the backend architecture across all product domains - define patterns, set standards, and ensure consistency across teams.
Lead architectural decisions from ideation through implementation, including design reviews and hands-on involvement when it matters.
Be the go-to technical authority for backend engineers across three teams.
Identify technical debt, scalability risks, and performance bottlenecks - and drive the roadmap to address them.
Partner with team leads to elevate engineering practices: code quality, testing, CI/CD etc.
Collaborate with product and R&D leadership to align technical strategy with business goals.

What You'll Do:
Realization and implementation of the architecture on the variety of technological components and services.
Implementation of automations and scripts based on Infrastructure As A Code (for example: Terraform).
Implementation and implementation of protection and security solutions in the cloud.
Maintaining regular interfaces with the security and cloud protection teams in the organization.
Locating and implementing new technological opportunities in the cloud field.
Maintaining regular interfaces with companies and organizations in the cloud field in Israel and in the community.

Workplace: Central area (access to the train).

Were hiring a QA Architect to join QA organization and lead quality strategy within a dedicated development group.

In this role, youll represent QA leadership inside the development group and act as the key quality partner for engineering and product leadership. Youll drive testing strategy, QA best practices, automation adoption, release readiness, and quality visibility across the group.

This is a hands-on leadership role, combining strategic quality ownership with active participation in feature testing, integration validation, and release activities.



What youll do

Own and drive the quality strategy for a dedicated development group.
Serve as the focal point for QA status, priorities, risks, blockers, and release readiness.
Define and enforce QA best practices, testing standards, and quality processes.
Lead testing activities, including planning, execution, regression, reporting, and release validation.
Partner closely with executives, developers, product managers, DevOps, QA engineers, and QA leadership.
Mentor and guide automation engineers.
Review test plans, test cases, automation coverage, and testing strategies.
Monitor quality KPIs, automation coverage, defect trends, and release confidence.
Promote automation reliability and expanded automation coverage.
Stay hands-on in testing, integration validation, and complex quality investigations.