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In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.

Key job responsibilities
Develop and design advanced semiconductor technologies for cloud infrastructure.
Collaborate on architecture definition and logic design for next-generation computing platforms.
Participate in comprehensive chip verification and bring-up processes.
Contribute to the entire product lifecycle from initial concept to mass production.
Support integration of new chip designs into AWS data center environments.

we are a leading Developer of microcontrollers and hardware security solutions for tier-1 customers in the computing and servers business. It is a self-contained design center, spanning from product management, system and chip architecture, through design, software development, system engineering and production flow development The group works closely with major customers, primarily key OEMs in the computing space, to develop semi-custom, innovative solutions for a wide range of application platforms. Our products combine unique sets of control, management and advanced security solutions, enabling our customer to establish differentiation in their end markets and bring value to their end customers. We are looking for an Engineering Project Manager (EPM) to lead our projects development. As an EPM you will manage and execute the development one or some of our projects from definition to production. You must possess a profound VLSI development knowledge, system understanding and high technical expertise along with strong management and leadership skills. You will be the head of a matrix-managed, multi-disciplinary team, working closely with all R&D groups as well as potentially external design service providers. You will build projects plan, define schedule and goals and maintain focus on projects budget and high quality standards. Main responsibilities: Lead Microcontroller projects life cycle from initial concept to mass production Manage the projects budget and schedule, set up development goals and track milestones execution while maintaining high technical and quality standards Lead cross-functional communication between the projects development teams to set and drive goals completion within schedule and quality standards Be the focal point for external multinational vendors and sub-contractors Proactively identify issues and work across organization and management layers to drive quick decisions Offering multiple levels of status to executive management

We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product.

Responsibilities
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip.

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part in flows development.

we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities


Execute the STA flow and sign-off methodologies, ensuring our products meet rigorous timing criteria for the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams, participating in timing reviews and working with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints, ensuring they are accurate and robust across multi-scenario environments
Analyze and resolve challenges related to cross-chip clock distribution networks and apply sophisticated margining techniques to ensure robust silicon across all process corners
Participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and custom scripts to make our sign-off process faster and more efficient

We are now looking for an outstanding, creative & hardworking Firmware PHY/Algorithms Engineer to join our team. You will be responsible for firmware development, characterization & validation of state-of-the-art network devices. Work as part of a team with circuit design, algorithm, architects & HW design to ensure outstanding product development from concept to customer satisfaction. The qualified candidate should be comfortable working on different code environments and should demonstrate a passion for the creation, execution, and improvement of FW features to control mixed-signal circuits.
What youll be doing:
Implement FW functionality in signal processing units of our products
Work closely with the architecture, HW, and SW design teams
Define implement and maintain FW algorithm to control the Silicon
Develop and test FW on emulation & simulation environments during the Pre-silicon phase
Debug and screen HW/FW/SW issues
Take an active part in silicon bring-up and SW development phases
Lead data-driven discussions about the product functionality and areas for improvement.

Required Embedded User Space Engineer
Description
We are a leading high-tech company, developing top-performing AI processors for edge devices in various industries. We combine an extensive understanding of the way neural networks operate, with our teams expertise in SW and HW architecture, to develop products that transform the way we use machines to perceive and analyze the world around us.
Our company is led by a group of experts from a wide range of disciplines, combining experience from elite intelligence units as well as leading tech companies in Israel and abroad, with a track record of executing complex projects from the ground up. As an AI chip company, we believe that AI can help us create a better, safer, more productive, and more convenient world. For this to happen, AI needs to be available at scale and on the edge.
To this end, our team of hardware and software leaders is developing top-performing AI processors, dedicated to AI tasks on edge devices in a wide variety of applications and industries including smart cities, automotive, manufacturing, agriculture, retail, and many more. With hundreds of customer programs around the world, and a wide ecosystem of software and hardware partners, we are leading the edge AI revolution.
In this position:
As a team member in our Media Pipeline team, you will be responsible for developing a C++ open-source framework and applications for our top-of-the-line AI-Vision processor. You will be working on a production-grade framework that enables Vision pipelines for our customers in multiple industries, such as security, automotive, retail and more.
If you are passionate about working with a large-scale SW and youre excited about AI, we want to meet you!
In this role, you will have a direct impact on our products.
Responsibilities
Help build and develop our best-in-class Edge AI SoC, developing an open-source, production-grade framework for the media pipeline
Work in different SW environments: C++, Python, C
Work closely with Software architects and the Machine Learning group, integrating and debugging complex software systems while taking into account challenging requirements as part of managing a large-scale embedded system.

Required Senior Package Layout Engineer
Our Networking unit has continuously reinvented itself over two decades. Our high-speed products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions. We're looking to grow our company and build our teams with smart people who can join us at the forefront of technological advancement. Our IC Packaging design team is looking for a Senior IC Packaging Design Engineer to join our package team. and focus on delivering and designing state of the art high-speed Interconnect systems for Supercomputers and Datacenters. This position will collaborate with Technical Package Lead and cooperation with different design teams and development of complex, detailed layout of IC substrates for our products.
What you'll be doing:
As part of a IC Packaging design team, you will collaborate to implement high speed and PDN design for ASIC packages.
Develop symbols, pad stack and perform substrate package routing, placement, stack-up, reference plane, power distribution using Cadence APD (Allegro) or SiP tools.
Optimize package pin out incorporating system level trade-offs of pins assignment.
Develop methodologies to improve layout environment, productivity, reliability, and schedule considerations.
In close co-operation with the SI/PI/HW design teams and product teams
Planning, ensuring stakeholder management and leading projects from start to finish.

Formulation, characterization design of solution architectures in the public cloud and integration into a team of architects.
Implement and execute the architecture across various technological components and services of cloud providers AWS/GCP.
Integrate security and protection solutions unto the architectures.
Guide and mentor project managers and developers in implementing the cloud architecture.
Maintain regular interfaces with companies and organizations in the cloud domain in Israel.
Implement automations and scripts based on Infrastructure AS A Code (e.g., Terraform).

Proactively acts as the voice of the customer/partner and internal communities leveraging relevant insights from feedback tools and systems. Proactively identifies and/or translates customer/partner problems into industry solutions. Drives self and guides other team members to focus on customer/partner experience through efficient delivery and ensuring a seamless and connected customer experience. Anticipates, identifies, escalates, and mitigates blockers using appropriate tools. Delivers solutions in line with company methodologies, ensuring proven practices and patterns are followed. Proactively identifies and anticipates new cross-solution opportunities for Consumption, Usage & Unified expansion at scale. Operates according to required operational excellence and proven practice standards throughout all sales stages/activities/tools of record. Leverages market insights and demand signals. Leads, mentors, and may assemble virtual teams using knowledge of our architectures and their context in the competitive landscape. Proactively identifies and anticipates gaps that enable solutions to scale across customers.

Responsibilities -

Business Impact,

Customer Centricity,

Partner Specialization,

Technical Leadership.

We're seeking a Staff engineer - AI Builder to lead the design and implementation of AI-native technical frameworks that redefine how large-scale systems are built, extended, and evolved.
This role is deeply technical and architecture-driven, focused on designing modular, extensible, and AI-first system foundations that enable scalable development with AI as a core engineering collaborator.
You will work across the full stack, building infrastructure where AI actively generates, extends, and maintains software components as part of the native development flow.
This is not about incremental AI integration - this is about architecting the frameworks that let AI scale software engineering 10x faster and smarter.
Responsibilities
Architect and lead the development of AI-native system frameworks that emphasize modularity, extensibility, and adaptive scalability.
Build platform primitives that enable dynamic AI-driven module and extension generation.
Design and implement developer workflows optimized for AI-assisted software development, embedding AI collaboration as a first-class design principle.
Define and codify AI-native engineering practices, patterns, and guidelines to elevate our software development lifecycle.
Establish and champion best practices for AI-assisted engineering across system design, code quality, testing, observability, and operational scalability.
Drive hands-on prototyping and iterative delivery across frontend, backend, and orchestration layers.
Provide technical leadership and mentorship, fostering an AI-first engineering culture across teams.
Partner closely with Product, AI, and Engineering teams to align system evolution with AI-native goals.

As a Senior/ Principal/ Senior Principal Software Engineer at Cortex Cloud, you will serve as a primary technical architect and visionary for our core communication infrastructure. This role is focused on the critical server-side backbone that facilitates high-scale bidirectional communication between our cloud services and client-side applications.
You will be responsible for the architectural integrity of systems that receive massive data inflows from the field and reliably broadcast intelligence back to millions of endpoints. This is a high-impact leadership role requiring a blend of deep technical mastery in distributed systems and the ability to influence technical strategy across the organization.
Key Responsibilities
Architectural Strategy & Vision: Define and drive the multi-year technical roadmap for our server-side communication infrastructure, ensuring the platform remains resilient and performant under extreme load.
High-Scale Communication Infrastructure: Lead the design and implementation of backend systems optimized for receiving high-scale data from client-side apps and distributing data back to a vast ecosystem of endpoints.
Technical Leadership & Influence: Act as a force multiplier by providing technical guidance to multiple engineering teams, aligning them on shared protocols, architectural standards, and communication patterns.
Drive Engineering Excellence: Champion a culture of high engineering rigor, focusing on deep observability, low-latency data distribution, and runtime stability for mission-critical production environments.
Cross-Functional Collaboration: Partner with Product Management, Infrastructure, and Client-Side Engineering teams to evaluate technical trade-offs, mitigate risks, and ensure seamless end-to-end data flow.
Innovation & Prototyping: Spearhead the evaluation of emerging technologies and lead "proof of concept" initiatives for next-generation transport layers and messaging paradigms.
Technical Mentorship: Invest in the growth of Senior and Staff engineers through deep-dive design reviews, code audits, and hands-on pair programming on the most critical paths.
Strategic Customer Engagement: Support the business by leading technical deep dives with strategic customers, translating complex architectural concepts into actionable confidence for our partners.

We are looking for a Director of Tech Strategy Labs to lead a group of architects to investigate and implement next-generation technologies, focusing on AI-native development, AI security, and enterprise SDLC, challenge existing solutions and standards, and harness your technology acumen to influence business strategy, innovation, and product roadmaps critical to the future of the Platform.
As a Director of Tech Strategy Labs, your work will influence thousands of companies using the Platform to drive their software release pipeline to create better value.
As a Director of Tech Strategy Labs at the CTO Office, you will...
Directly manage the CTO Office architects
Manage selected software development projects end-to-end with the highest quality
Explore, evaluate, and prototype new and differentiating products and capabilities enabled through emerging technologies, leading techniques, and contemporary patterns to create our next world-class solutions and experiences
Help identify research opportunities and drive innovation, coming from understanding our vision, the problems we are set to solve, the pain of our customers, the voice of market analysts and partners
Partner with community working groups and initiatives, such as those led under the CNCF
Maintain a deep understanding of the architecture of new and existing solutions under the Platform and how they interoperate
Work closely with the CTO, Product, Developers, Sales Engineers, Security, and Business Strategy teams to achieve common goals
Challenge existing architecture and solutions to improve customer experience, increase efficiency, reduce risk, increase resiliency, and improve performance
Provide technical leadership by synthesizing and communicating complex information being researched, and advance the topics mentioned above
Advocate clean code and clean architecture principles, and ensure documentation with proper technical specifications.