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Key job responsibilities
* Daily involvement in all aspects of physical design chip development (RTL2GDS), including floorplanning, synthesis, clock tree synthesis, place and route, static timing analysis, power and noise analysis, physical verification testing, and equivalence checks.
* Being actively engaged in design-backend convergence aspects and defining timing constraints.
* Taking full end-to-end responsibility for the physical design of macro and cluster-level blocks, according to specifications, under challenging constraints, with focus on optimizing power, area, and performance.
* Participation in the development of design flows, using a variety of EDA tools and vendors such as Synopsys and Cadence.
* Engaged in defining implementation and signoff methodologies.

Required Design Verification Vision Lead, Cloud.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive cutting-edge distributed inference technology that powers real-time systems where latency and reliability are mission-critical.

You will be part of a team that pushes boundaries, developing robust, autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.

Required Physical Designer Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Define and drive the implementation of physical design methodologies.
Take ownership of one or more physical design partitions or top level.
Drive to the closure of timing and power consumption of the design.
Contribute to design methodology, libraries, and code review.
Define the physical design related rule sets for the functional design engineers.

we are looking for a Physical Design Manager.
You'll be part of the Cisco Silicon One team, which is at the heart of Ciscos software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff / Principal ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.
As a Staff / Principal ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams
Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities
Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration.

Our Networking IC Product Engineering team is looking for a Post Si Characterization and Validation engineer, to take part of Network ASIC, SOC and SiPh ICs characterization efforts of speed, logic, memory, power and analog circuits both using ATE and system level testing. We are in need of hardworking and motivated engineers. Do you have passion for data analysis, post-Si hand on work and problem solving? We will be happy to have you on our team!

What you'll be doing:

The position includes taking ownership of characterization of IC performance and power parameters, developing new characterization and analysis capabilities, enabling the qualification of new and improvement of future products. You will define and build the required tests, perform the analysis and present the results and conclusions to a wide forum including leading designers and high-level executives.

Take important part in definition of requirements for post-SI validation, as well as IC power and performance characterization.

We offer an exciting work environment, with many new learning experiences and interactions with people from different aspects of the company. Our company employs some of the best engineers in the communication field from all across the world, working on innovative technology and developing new and daring projects.

We are searching for hardworking engineers, that will lead new projects starting from the product definition phase, until the mass-production phase, working closely with several other teams, including chip design, power architecture, and BE.

Our Networking IC Product Engineering team is looking for a Post Si Characterization and Validation engineer, to take part of Network ASIC, SOC and SiPh ICs characterization efforts of speed, logic, memory, power and analog circuits both using ATE and system level testing. We are in need of hardworking and motivated engineers. Do you have passion for data analysis, post-Si hand on work and problem solving? We will be happy to have you on our team!


What you'll be doing:

The position includes taking ownership of characterization of IC performance and power parameters, developing new characterization and analysis capabilities, enabling the qualification of new and improvement of future products. You will define and build the required tests, perform the analysis and present the results and conclusions to a wide forum including leading designers and high-level executives.

Take important part in definition of requirements for post-SI validation, as well as IC power and performance characterization.

We offer an exciting work environment, with many new learning experiences and interactions with people from different aspects of the company. Our company employs some of the best engineers in the communication field from all across the world, working on innovative technology and developing new and daring projects.

We are searching for hardworking engineers, that will lead new projects starting from the product definition phase, until the mass-production phase, working closely with several other teams, including chip design, power architecture, and BE.

Required Staff RTL IP/Component Design Engineer, Cloud
About the job
In this role, you will contribute in all phases of complex application-specific integrated circuit (ASIC) designs from design specification to production. You will collaborate with members of architecture, software, verification, power, timing, synthesis and etc. to specify and deliver high quality SoC/RTL. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next-generation of our platforms, we make product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Define the block level design document such as interface protocol, block diagram, transaction flow and pipeline, etc.
Perform RTL development (e.g., coding and debug in Verilog, SystemVerilog, and VHDL), function/performance simulation debug and Lint/CDC/FV/UPF checks.
Support synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

Semi Conductor Devices (SCD), a leading worldwide supplier of high-end Infrared Detectors and thermal imaging cores, is looking for an Analog / Mixed-Signal VLSI Designer to join its VLSI R&D group. The role involves design and validation of custom analog and mixed-signal ASICs (ROICs) for advanced IR imaging systems, working closely with experienced analog, digital, system, and hardware teams.
Responsibilities:
Design and verify Analog and Mixed-Signal circuit blocks for IR image sensors (ROICs) under the guidance of senior designers Participate in the full ASIC development flow: specification review circuit design verification integration silicon bring-up lab validation Contribute to block-level simulations, documentation, and design reviews Work closely with digital designers, layout engineers, electronics, and system teams to support chip integration Support post-silicon validation and lab measurements, including debug and correlation to simulations Gain exposure to advanced CMOS processes, image sensor architectures, and system -driven design constraints.

You will manage the AI Platform Engineer(s), set the technical standards for the AI Power User group's citizen development program, and serve as the connective tissue between business leadership, platform owners, and development teams. You will shape the multi-year AI architecture roadmap while also rolling up your sleeves to conduct architecture reviews, resolve blockers, and move use cases from concept to production. This is a role for someone who can think big and execute - and who understands that in an enterprise context, the quality of your governance is inseparable from the quality of your architecture.

What You'll Own
Strategy & Architecture
Define and own the enterprise AI integration strategy - identifying opportunities to embed intelligent automation, agentic workflows, predictive analytics, and generative AI capabilities across our company core platforms
Develop and maintain reference architectures, design patterns, and the AI architecture decision log that governs how AI models connect to enterprise systems and what they are permitted to do
Consult on enterprise system architecture and implement best practices for the Enterprise Business Systems team to leverage in their day-to-day execution.
Lead Proof-of-Concept initiatives for new AI tools and platform-native AI features, evaluating them against build-vs-buy criteria before recommending adoption
Partner with business stakeholders to translate operational pain points into AI use cases with clear ROI framing and sequencing criteria
Contribute to our enterprise data strategy, ensuring AI initiatives are supported by clean, accessible, and well-governed data pipelines
Integration Architecture & Delivery

Design and own the Workato eMCP layer - the MCP governance model, persona-scoped token framework, workspace isolation strategy, and the single sanctioned action surface through which all AI agents write back to enterprise systems
Define integration patterns and standards for AI model connectivity (Claude, ChatGPT) to Salesforce, NetSuite, HiBob, and Jira - specifying what agents can read, what they can write, through which surfaces, and with what confirmation and audit requirements
Design and oversee API strategies, event-driven architectures, and middleware patterns that support scalable AI feature delivery - including agentic workflows, intelligent data transformation, anomaly detection, and natural language interfaces layered onto ERP and CRM data
Collaborate with Engineering during build phases, conducting architecture reviews, providing hands-on guidance, and resolving complex technical blockers
Define non-functional requirements - latency, security, auditability, model drift monitoring - for AI components embedded in mission-critical business processes
Establish MLOps and LLMOps practices appropriate for our enterprise environment: model versioning, observability, and rollback procedures for production AI workloads

we are looking for a hands-on Tech Lead to join our R&D. Reporting directly to the Chief Architect, you will step into a rare opportunity with a fast-growing company to shape the technical future of our platform. You will serve as a technical anchor for the organization, driving the architectural evolution of our high-scale, cloud-native infrastructure built on AWS and Kubernetes, while pioneering the integration of AI across our product and engineering workflows.
Responsibilities:
Drive the technical roadmap for Firefly's platform, working closely with the Chief Architect: architecting new systems and features and continuously improving existing ones.
Lead architectural decisions across the platform's core surfaces: services, data pipelines, workflow orchestration, and multi-tenant infrastructure.
Stay hands-on in the code: build critical components, prototype new capabilities, and lead by example inside the development teams.
Establish the platform foundations: shared services, libraries, and standards used across teams.
Architect AI-powered capabilities into Firefly's product and drive AI-assisted development workflows that amplify engineering productivity across the org.
Drive end-to-end technical solutions, from API design and service boundaries to data modeling and deployment.
Build proofs-of-concept for critical paths and high-risk decisions, and act as the technical anchor for projects from design through delivery.
Write design documents, RFCs, and architectural decision records that drive cross-team alignment and capture the reasoning behind technical decisions.
Mentor engineers across teams through design and code reviews, and act as a focal point for technical questions across R&D.

we are seeking a skilled Salesforce Solution Architect to join our team. As a Salesforce Solution Architect, you will design and implement Salesforce solutions for our clients. You will collaborate with various stakeholders to understand business requirements and translate them into scalable and efficient Salesforce solutions. The ideal candidate will have a solid technical background in Salesforce, with demonstrated expertise in architecture design and implementation. We want to hear from you if you are passionate about Salesforce and enjoy working in a dynamic and challenging environment.
Responsibilities:
Designed and implemented Salesforce solutions for clients, ensuring scalability, efficiency, and best practices
Collaborate with stakeholders to understand business requirements and translate them into technical solutions
Lead and participate in project planning and estimation activities
Provide guidance and mentorship to development teams on Salesforce best practices and design patterns
Collaborate with cross-functional teams to integrate Salesforce solutions with other systems
Identify and resolve technical issues and challenges, driving continuous improvement and optimizing Salesforce solutions
Stay up-to-date with Salesforce platform updates, new features, and industry trends to provide innovative and effective solutions
that is used for creating requisitions 'from scratch'.

As our Head of R&D, you will bridge the gap between high-level architectural vision and day-to-day execution. You are a player-coach who isn't afraid to dive into the code while leading our engineering efforts to build, scale, and optimize our AI-driven dating platform.
What You'll Do:
Be a Hands-on Lead Architect: Architect, develop, test, and document core components. You will code alongside the team, ensuring high-quality, scalable solutions
Lead & Grow the Team: Manage and mentor a high-performing cross-functional team of 4 (FE, BE, QA)
Bridge Technical & Business Worlds: Act as the technical partner for Product, Design, and Marketing. Translate business requirements into technical reality while ensuring seamless collaboration across all departments
Own the Tech Lifecycle: Lead the full SDLC, from AI feature implementation and infrastructure (AWS) to CI/CD and production deployment

Were looking for a Solutions Architect Team Lead to manage, recruit, and mentor our Israeli and CEE Solutions Architects, as well as provide core services and also to provide technical pre-sales guidance to our company customers while building long-term relationships, identifying pain points, and addressing them.
Work location: hybrid from Tel-Aviv
Curious about what it's really like to work at our company?
Explore our benefits, culture, and what success in your first year could look like here.
If you are interested in this opportunity, please submit your CV in English.
Key Responsibilities
Meet with customers, understand their business challenges, and design AWS solutions that address them, covering architecture, cost-efficiency, scalability, and security through Statements of Work (SOW)
Manage and mentor a team of Solutions Architects, including mentorship, professional team growth, recruiting and interviewing, and supporting the broader department's team expansion efforts.
Analyze existing customer AWS architectures and propose improvement roadmaps
Collaborate cross-team with different departments to ensure solutions are designed according to AWS best practices
Build thought leadership in the cloud community by contributing to blogs, workshops, webinars, conferences, and more, representing our company as a trusted voice in the ecosystem
Travel both locally (to meet with customers, partners, and attend local events) and abroad (at least once a quarter)
Build a strong relationship with the AWS Startup SA community.