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We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up.

As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You wont just be using tools; youll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors.


Key Responsibilities
Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes.
Create robust applications using Python and Tcl to automate models build, regression and analysis tools and other assisting tools for all disciplines in front-end flows.
Evaluate and integrate Electronic Design Automation (EDA) tools from vendors like Cadence, Synopsys, and Mentor Graphics.
Define the methodologies of usage and integrate AI tools in this fast-growing field impacting all VLSI development flows.

As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters.

As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You wont just execute tasks; you will define the Formal verification strategy for chips that drive the worlds largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications.

Key Responsibilities
Own and develop formal verification environments from scratch through to sign-off.
Apply formal verification methodologies and strategies to prove the correctness of intricate designs.
Work closely with the Architecture, Design, and DV teams to identify verification needs and pinpoint design requirements.
Create robust formal environments, analyze complex RTL designs, and apply advanced formal techniques to find corner-case bugs.
Analyze verification results, identify failures, and collaborate directly with designers to resolve issues efficiently.
Architect and develop generic, common formal functions and properties to be reused across multiple projects.

As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Senior Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging.
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies.
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market.

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs.
Ensure rapid cycles from RTL to functional stability through systematic debug approaches.
Own technical blocks and drive them to completion independently.

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios.
Ensure seamless hardware-software integration for AI infrastructure connectivity.
Collaborate with Design and Verification teams to optimize emulation strategies.

As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks.
Develop and maintain System Verilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing.
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified.

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process.
Drive designs toward 100% verification closure through comprehensive test development.
Contribute to verification methodology improvements and best practices.

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle.
Apply analytical skills and debugging techniques to solve intricate verification challenges.
Collaborate effectively in a fast-paced, team-oriented R&D environment.

As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects.

As a Senior ASIC Design Engineer, you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into elegant, high-performance hardware. If you thrive on solving challenging problems in deep-submicron processes and want to contribute to the digital design foundation for AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Design Ownership & Implementation
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
Serve as the point of contact for your logic blocks, interacting with Architecture, Verification, and Backend teams

Quality Assurance & Design Optimization
Utilize industry-leading EDA tools (Lint, CDC, Synthesis, Timing, Power) and in-house quality assurance tools to ensure designs are robust, scalable, and power-efficient
Apply design techniques to meet PPA (Power, Performance, Area) targets
Contribute to design quality through verification and validation activities

Methodology Innovation & Collaboration
Participate in design methodology improvements and tool automation initiatives
Leverage AI assistance tools and contribute to in-house automation development to make engineering workflows faster and smarter
Collaborate effectively across teams to ensure seamless integration

As we expand our presence in Israel, we're seeking a talented Principal Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters.

As an Principal Emulation Engineer, you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges and want to play a key role in validating cutting-edge AI infrastructure connectivity solutions, this is your opportunity.

Key Responsibilities

Emulation Flow Execution & Implementation
Execute end-to-end emulation flow from high-level model generation and RTL synthesis to complex system-level testing and silicon-accurate debugging
Work directly with next-generation emulation platforms (Zebu, Palladium, or Veloce) to implement cutting-edge methodologies
Maintain and evolve emulation flows to reduce compile times and increase execution speed, directly impacting time-to-market

System-Level Debug & Validation
Drive initial model bring-up process in high-stakes environment, identifying and resolving complex bugs
Ensure rapid cycles from RTL to functional stability through systematic debug approaches
Own technical blocks and drive them to completion independently

Cross-Functional Collaboration
Partner with Firmware, Software, and Validation teams to debug complex system-level scenarios
Ensure seamless hardware-software integration for AI infrastructure connectivity
Collaborate with Design and Verification teams to optimize emulation strategies

As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and teams.
This is a critical leadership position with high impact on first-pass silicon success and production quality for next-generation AI connectivity solutions.
Key Responsibilities

DFT Architecture & Technical Leadership
Define and own DFT architecture for complex SoCs, including Scan, MBIST, LBIST, JTAG/iJTAG, and ATPG strategies.
Lead DFT planning, specification, and quality tracking across the project lifecycle.
Provide technical leadership and drive DFT sign-off readiness to ensure successful tapeout.

Execution Across the Full Lifecycle
Lead DFT implementation, integration, and verification at block, full-chip and chiplet levels.
Own end-to-end DFT activities from specification through silicon bring-up and production support.
Ensure high test coverage, robust pattern generation, and alignment with manufacturing requirements.

Methodology & Cross-Functional Impact
Develop and drive scalable DFT methodologies, flows, and automation frameworks.
Collaborate closely with RTL, Physical Design, STA, and Test Engineering teams to ensure design-for-test readiness.
Optimize DFT integration across front-end and backend flows to improve quality, PPA, and turnaround time.

We are seeking an experienced Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems.
This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design. You will play a key role in shaping innovative solutions that enable hyperscale customers to build scalable, high-bandwidth, and low-latency systems.

This is a unique opportunity to join a new and growing Israel site, influence technical direction, and take ownership of critical architectural decisions impacting industry-leading products.

Key Responsibilities
Define and drive system and chip-level architecture for high-speed connectivity products.
Lead architecture for PCIe-based interconnects, networking protocols, and Ethernet subsystems.
Analyze system requirements and translate them into scalable and efficient hardware architectures.
Drive tradeoff analysis across performance, power, latency, area, and cost
Collaborate with cross-functional teams including RTL, Physical Design, Firmware, Validation, and Product Engineering.
Define and review micro-architecture specifications and ensure alignment across teams.
Contribute to standard-based and custom protocols for next-generation AI infrastructure.
Support performance modeling, simulation, and architectural validation.
Work closely with customers and partners to understand emerging use cases and requirements.
Mentor engineers and help build strong technical leadership within the Israel R&D center.

Were hiring an AI Backend Engineering Manager to guide and grow a high-impact ML team driving AI-powered innovation across B2B SaaS platform. Youll lead the design and delivery of AI solutions while mentoring engineers and setting the technical direction for AI-first development at scale.
This is a leadership role with a balance of hands-on engineering and team management, perfect for someone who thrives on solving technical challenges, inspiring a team, and shaping the future of AI in fintech automation.
What You Will Do:
Lead & Mentor: Manage, mentor, and grow a team of AI/ML/Backend engineers, fostering technical excellence and career development.
Set Technical Direction: Define the ML strategy, ensuring best practices in architecture, frameworks, and operationalization.
Build and deploy AI-based solutions: Oversee the development and deployment of GenAI/LLM-powered solutions that address real-world challenges across products.
Scale & Operationalize: Establish scalable ML infrastructure, CI/CD, observability, and data pipelines for high-availability production systems.
Collaborate Cross-Functionally: Partner with product managers, engineers, and business stakeholders, clearly communicate progress, challenges, and outcomes.

We are looking for a Post-Silicon Validation Engineer with strong hands-on experience in PCIe link bring-up, physical-layer debug, and silicon validation. Engineer will work closely with Design, Architecture, Firmware, Software, Engineering teams.

Key Responsibilities
Perform hands-on post-silicon validation
Debug PCIe link issues including link training, LTSSM, equalization, recovery, resets, and link stability.
Analyze PCIe state-machine traces, protocol traces, registers, logs, eye diagrams, and lab measurements.
Drive complex issues from initial failure through root-cause analysis and final resolution.
Work closely with silicon, firmware, software, architecture, and signal-integrity engineers to isolate issues across HW/FW/SW boundaries.
Validate PCIe functionality across different generations, platforms, configurations, and operating conditions.
Develop and execute PCIe validation plans, stress tests, corner-case scenarios, and interoperability tests.
Develop automation to improve validation coverage, debug efficiency, and regression testing.

we are seeking a Full Stack Team Lead to drive AI-first development across our core platform.
As an AI-first company, we integrate artificial intelligence into every facet of our operations, from product development to internal processes. In this role, you'll lead a team of 5-6 dedicated full-stack developers, working on cutting-edge technologies to enhance user experiences and data-driven solutions.
You'll have the autonomy to make technical decisions and support other developers in a collaborative environment.
What You Will Do:
Lead Development Initiatives: Guide a team of full-stack developers in building core applications, ensuring the integration of AI-driven features.
Mentorship: Provide technical guidance to engineers, fostering their growth and promoting best practices in AI-assisted development.
Architectural Decisions: Make hands-on technical decisions for backend (Java + AWS) and frontend (React/Angular) components, incorporating AI tools where applicable.
Code Quality: Write clean, maintainable, and efficient code, setting high standards for code quality and review practices.
Cross-Functional Collaboration: Work closely with Product teams to prioritize features, estimate work, and keep projects on track, leveraging AI to streamline processes.
Innovation: Identify pain points and drive improvements in our codebase and processes, utilizing AI to enhance efficiency.
Team Motivation: Ensure daily alignment, remove blockers, and champion best practices within the team.

As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team.

This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career.


Key Responsibilities

Guided Implementation & Learning
Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning, Place & Route (P&R), and Clock-Tree Synthesis (CTS).
Assist in macro-level implementation and develop hands-on skills in complex layout routing.
Participate in deep-submicron process challenges under close professional mentorship.

Signoff & Design Integrity Support
Assist in running engineering checks for design integrity, including Static Timing Analysis (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR).
Learn to apply Logic Equivalence Checking (LEC) to help guarantee design correctness.
Gain exposure to the rigorous flows required to ensure first-pass silicon success.

Scripting & Cross-Functional Collaboration
Leverage and develop scripting tools to automate repetitive tasks and optimize the engineering environment.
Collaborate with Architecture, Design, and DFT teams to understand how different chip design disciplines intersect.
Actively participate in team reviews and technical discussions to ramp up backend methodologies.

Were hiring a ML Engineer to accelerate AI-driven innovation across B2B SaaS platform.
Youll be at the forefront of building intelligent systems that power core product experiences and automate internal operations, driving efficiency, speed, and scale across the organization. This is a high-impact, hands-on role in a fast-growing, AI-first company where machine learning is a foundational pillar, not a bolt-on feature. You'll partner with product, engineering, and operations teams to design and implement powerful ML and LLM-based solutions that make a measurable difference.
What You Will Do:
Build Intelligent Systems: Design and develop ML/LLM-powered solutions that solve real-world challenges across product and internal workflows.
Own Full Lifecycles: Take projects from concept all the way to production, including model training, evaluation, integration, and monitoring.
Leverage State-of-the-Art Tools: Work with leading frameworks like LangChain, Hugging Face, TensorFlow, and PyTorch to deliver cutting-edge functionality.
Collaborate Cross-Functionally: Partner with product managers, engineers, and stakeholders to embed AI capabilities into user-facing features and backend services.
Ship at Scale: Build and maintain scalable APIs and services, integrating best practices in CI/CD, observability, and cloud infrastructure.
Report with Impact: Share progress, challenges, and results clearly with technical and executive stakeholders.

We are hiring a Manager Design Engineer to help architect and deliver the connectivity silicon powering the world's largest AI clusters. You'll own design execution on complex blocks across our purpose-built products, working at the cutting edge of PCIe, CXL, Ethernet, and emerging rack-scale interconnect technologies.

This is a high-impact technical role at a hyper-growth company. You'll partner closely with architecture, verification, DFT, and physical design teams to take features from spec to silicon, while contributing to the design methodology that scales with our roadmap. If you want to ship silicon that defines AI infrastructure, this is the team.

Key Responsibilities

RTL Design & Implementation
Own RTL design for assigned blocks from microarchitecture through synthesis sign-off.
Develop high-quality, synthesizable Verilog/SystemVerilog with strong attention to PPA.
Drive design reviews, lint, CDC, and timing closure activities to silicon-ready quality.

Cross-Functional Execution
Partner with architecture to translate specifications into implementation-ready microarchitecture.
Collaborate with verification on testplans, coverage closure, and bug triage.
Work with DFT and physical design teams on scan, BIST, floorplanning, and timing closure.

Technical Leadership & Quality
Mentor junior engineers and contribute to design methodology, scripts, and best practices.
Debug complex pre-silicon and post-silicon issues across RTL, gate-level, and emulation environments.
Drive structured, data-driven design decisions in support of aggressive tapeout schedules.