לוח משרות דרושים בגבעתיים

We are looking for an experienced and strategic Learning & Organizational Development (OD) Lead to join our human resources team. In this pivotal role, you will partner closely with senior leaders and key regional stakeholders to identify development needs and opportunities. You will design and lead an organizational development strategy and roadmap to build leadership capabilities, drive talent management, and foster a high-performance culture aligned with business goals all while placing a strong emphasis on elevating the overall employee experience and supporting our growth and innovation.

Responsibilities:
Develop and execute a multi-year global organizational development strategy aligned with the company's overall business goals.
Manage the full lifecycle of major organizational development initiativesfrom needs assessment and strategic design to implementation, communication, and impact measurement.
Oversee leadership development across the company, shaping global programs and tailoring local initiatives.
Lead company-wide cultural transformation efforts to foster a collaborative, high-performing, and continuously improving work environment
Provide expert organizational development consulting and advisory support to HR business partners and business leaders on people and organizational topics.
Use data, assessments, benchmarks, and best practices to continuously enhance organizational development strategies and solutions.

We are seeking a Senior HPC Application Engineer with extensive experience in running, profiling and optimizing benchmarks and HPC applications at the server or cluster level. As part of the System Performance software team, you will play a pivotal role in analyzing and improving key HPC applications, directly influencing software requirements and hardware specifications. This position sits at the intersection of computer science and computational physics, requiring both technical expertise and creative problem-solving to address bottlenecks and accelerate application performance on novel architectures. If you are passionate about science, skilled at tackling complex challenges, and thrive in a cutting-edge multidisciplinary environment, we want to hear from you!

Responsibilities:
Profile a wide range of HPC applications on various architectures, identifying performance bottlenecks.
Develop creative algorithmic and software solutions to address bottlenecks and accelerate applications on a novel dataflow architecture.
Translate application requirements into software features and hardware requirements.
Develop performance models for future hardware architectures.

The AI software team is building solutions that enable the latest AI models and workflows to run efficiently on on NextSilicons unique hardware architectureunlocking a new level of performance

We are seeking a talented engineer with extensive experience in modelling, analyzing and optimizing AI workloads and end-to-end flows. This position lies at the intersection of computer science, hardware architecture and ML computational algorithm.

Responsibilities:
Model AI workload behavior on custom hardware and software
Identify bottlenecks and propose optimizations in hardware architecture and software.
Define next generation software requirements and specifications.

As part of the memory system team, you will work on design and implementation of new and enhanced features of the memory system to support high performance computing and AI applications in the Maverick accelerator runtime environment.

You will work closely with software engineers, hardware engineers, compiler developers and other stakeholders to enable the most efficient execution of applications on a large scale, multi threaded and highly distributed system across multiple disciplines with a deep OS Internals point of view.

Responsibilities:
Work on design and implementation of new and enhanced features of the memory system for the Maverick accelerator.
Develop a high performance, low latency distributed unified virtual memory management system.
Work on system software support for the next generation Maverick system.
Define feature development scope and plan for successful product delivery.
Wide system impact through collaboration with software engineers, hardware engineers, compiler developers and other stakeholders.

We are looking for a talented and experienced Group Manager to lead teams in our software division, building an innovative multidisciplinary computing platform. In this role, you will bridge the gap between architecture, software, and hardware. You will lead the development of the lower layers in our highly optimized software stack including Boot, BSP, and device runtime, while dealing with an innovative and challenging system architecture.

Responsibilities:
Work on design and implementation of new and enhanced runtime features across the AI stack to support high performance computing of AI models.
Develop the runtime environment for massively accelerating AI workloads execution and handle OS/device process and thread lifecycle.
Develop multi nodes execution scaling while leveraging standard networking APIs of MPI and Collectives.
Define feature development scope and plan for successful product delivery.
Wide system impact through collaboration with software engineers, hardware engineers, compiler developers and other stakeholders.

We are looking for an experienced STA Engineer to join our growing BE team. We are working on the most challenging and interesting ASIC chips. Come join us and have a big impact on our groundbreaking and innovative designs.

Responsibilities:
Take part in STA activities for blocks, Sub Systems and Full chip, from definitions to TO.
Analyze timing results, verify correctness and provide timing budget for the different partitions.
Own the timing constraints both for STA and P&R flow.
Working closely with architecture, design, PD and DFT teams to make sure timing closure and ensures product success.
Identify risks and bottlenecks, work closely with PD, RTL and DFT teams, ensuring convergence throughout various project stages.
Participating in design methodology, reviews and tool automation work and definition.
As part of this rule you will gain very good understanding of our HPC and AI designs and sub system as well as product targets.

We are looking for a talented and experienced Physical Design lead to take part in the physical design and help lead the companys BE activities . This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on our final product.

Responsibilities:
Lead blocks and sub systems execution from RTL to GDSII.
Clearly reflect status and execution metrics and help identify and solve execution bottlenecks.
Spec and define full floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines
Perform critical block-level place and route and create designs that meet PPA targets.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip.

We are looking for a talented and experienced engineer to participate in the physical design of the companys product for leading one of our BE projects. This position involves working with external back-end developers as well as carrying out critical tasks in-house, and leading aggressive back-end initiatives to meet challenging targets in terms of area, timing, and layout. In this role, you will be at the center of the companys design efforts and will have a significant influence on product architecture.

Responsibilities:
Generate and analyze critical block- and chip-level static timing constraints.
Spec and define full chip floor plan, including pin placement, partitions, and power grid.
Develop and validate high-performance, low-power clock network guidelines.
Perform critical block-level place and route and create designs that meet timing, area, and power constraints.
Review the vendors physical design verification flow at chip and block level and guide other designers on how to fix LVS and DRC violations.
Work with vendors on defining physical design methodologies and assist in flow development for chip integration.