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Location: Tel Aviv-Yafo
Job Type: Full Time
about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
our mission at our company system infrastructure is to build the best cloud in the world for our company services and for our company cloud customers, by solving real world business challenges of performance, cost, and scale, utilizing hardware, software, and system solutions. to better serve evolving cloud needs, our company is establishing a team in israel to develop custom chips for servers.in this role, you will perform formal verification of design properties of complex asic designs. you will collaborate closely with design and Verification engineers to define meaningful properties that capture the design intent of a logic block and constraints on its input stimulus. you will also help define and improve design and verification methodologies that allow you to achieve formal verification closure. our company's mission is to organize the world's information and make it universally accessible and useful. our team combines the best of our company ai, software, and hardware to create radically helpful experiences. we research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. we aim to make people's lives better through technology.
responsibilities
plan the formal verification strategy and create the properties and constraints for complex digital design blocks.
utilize formal property verification tools combined with formal verification closure techniques to verify properties.
resolve difficult to verify properties. contribute improvements to methodologies to enhance formal verification results.
architect and implement reusable formal verification components.
Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, Computer Science, or equivalent practical experience.
8 years of experience working on main interconnects, direct memory access (dma), controllers, and power management.
experience capturing design specification in a temporal assertion language such as sva or psl.
preferred qualifications:
master's degree or phd in electrical engineering or Computer Science.
2 years of experience working on main interconnects, direct memory access (dma), controllers, and power management.
experience working with one or more formal verification tools, such as jaspergold, vc formal, questa formal, or 360-dv.
understanding of formal verification algorithms.
proficiency with scripting languages, such as Python.
This position is open to all candidates.
 
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22/03/2026
Location: More than one
Job Type: Full Time
Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.
Requirements:
What We Need to See:

Bachelors or Masters Degree in Electrical Engineering, Computer Science, or equivalent experience.

7+ years of hands-on pre-silicon verification experience, with a strong foundation in Formal Verification (FV).

A perspective geared toward automation and experience, defining or refining complex verification infrastructures.

A desire to redefine traditional "manual" verification workflows using modern software and AI principles.

Ways to Stand Out from the Crowd:

Experience building or deploying AI tools specifically designed for hardware (e.g., LLM-based assertion generation)

Proven track record of collaborating with CAD or tool-development teams to refine internal design flows.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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22/03/2026
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are seeking a Principal verification engineer to be a technical lead in the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and adopting new technologies. One of our main goals is to define, build and use best in class technologies make sure that the chip design team works in an efficient manner and provides high-quality deliveries at scale. This position offers the opportunity to drive foundational flows and have a profound impact in a dynamic, technology-focused company.

What you'll be doing:

Define groundbreaking methodologies to create a flawless experience for verification engineers.

Mentor and guide designers and verification specialists to tackle complex technical challenges.

Identify design risks, define the verification scope, and lead infrastructure development to ensure design correctness.

Technically guide the development process of shared verification code and infrastructure to be widely used by the global chip design team.

Partner with the design automation team to provide end-to-end solutions that unify verification, simulation, and automation.

Collaborate with EDA vendors to learn about innovative tools/technology and integrate them into our long-term verification strategy.

Lead verification strategies, training sessions.
Requirements:
What we need to see:

A Bachelors Degree in Electrical Engineering or Computer Science, or equivalent experience.

Comprehensive mastery of design and verification tools.

15+ years of hands-on pre-silicon verification experience with a track record of technical leadership.

Exceptional interpersonal skills and ability & proven track record to promote innovation.

Ways to stand out from the crowd:

Experience leading processes across multiple groups and driving meaningful, influential change in the verification lifecycle.

Deep knowledge of simulation tools and performance optimization.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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19/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking Switch technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our Switch team delivers world class Bridge and router solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver smart and high bandwidth multi port switches. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

You will work on developing new formal verification methodologies and tactics.
Requirements:
What we need to see:

BSc in Electrical/Computer Engineering or MSc in Mathematics.

1+ years of experience

Excellent analytical, logical reasoning and problem-solving skills.

Strong debugging and analytical skills.

Strong communication and interpersonal skills are required.

Ways to stand out from the crowd:

Formal verification work experience.

Knowledge of digital logic.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8585223
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18/03/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a best-in-class Chip Design Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer in our GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry - our GPU Super-Chip.

What youll be doing:

Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU.

Integrations and Full-Chip models.

Verification of chip blocks/entities according to specifications under challenging constraints.

Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration.
Requirements:
What we need to see:

3+ years of experience in RTL design verification.

B.Sc. in Electrical Engineering or Computer Engineering.

A team player with good communication and interpersonal skills.

Ways to stand out from the crowd:

Background in Specman and System-Verilog UVM.

Knowledge in Networking.
This position is open to all candidates.
 
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