לוח משרות דרושים מהנדס מחשבים בתל אביב יפו

We are seeking a highly motivated Embedded Software Team Leader to own the execution of key components within the DPU BMC system. Seeking a candidate proficient in software development of embedded systems, taking ownership for team's tasks. Collaborate with team leaders, various teams, and customers to improve our product.


What you'll be doing:

Lead and manage a team of embedded software engineers, providing both personal and professional mentorship.

Drive the execution of assigned components from conception to delivery, ensuring timely software milestones and contributing to overall product releases.

Coordinate with peer team leaders to ensure seamless integration across the broader DPU system.

Engage in hands-on embedded software development using C/C++.

Establish and lead all developments and methodology aspects and process.

Take ownership for delivering functionality, stability, and performance of the system.

Collaborate closely with internal cross-functional teams and peer leaders (architecture, hardware, firmware, validation, product management).

Work directly with external customers to understand system requirements, use cases, and provide technical support.

We are seeking a passionate and innovative Senior Software Engineer with expertise in enterprise and data center networking to join our Cumulus Linux team. Cumulus Linux is a leading open-networking operating system and a cornerstone of the AI Factory - the next-generation data center designed to power the training, fine-tuning, and deployment of AI models at scale. As part of the team, you will design and implement core features of Cumulus Linux that enable the worlds most advanced data centers. You will work closely with cross-functional architecture and design teams, shaping the future of our networking technologies while gaining hands-on experience across our hardware and software ecosystem - from advanced networking ASICs to large-scale distributed systems.

What you'll be doing:

Design, develop, integrate, and test data forwarding and routing features in our Cumulus Linux.

Enable our Cumulus Linux on next-generation ASICs.

Work collaboratively with team members, product managers, architects, QA, and other engineering teams to deliver high-quality solutions.

Innovate and rapidly develop proof-of-concept (POC) prototypes that can evolve into fully developed products or solutions.

Engage closely with customers to understand their challenges, use cases, and deployment strategies, and devise innovative solutions.

We are looking for best-in-class Physical Design Power Engineer to join our outstanding Networking Silicon Power engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput, lowest latency and best Power! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you will be doing:

Power Optimization of Physical design, of blocks/top-level/fc under challenging constraints.

Optimization involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise fixes.

Power estimation and power modeling.

We are seeking a highly skilled and proactive Senior Cyber Security Threat Intelligence (CTI) Analyst to join the Networking product security team. In this critical role, you will function as a key defender of the technologies powering the worlds largest AI clusters. You will act as the eyes and ears of our product security organization, conducting investigative research into sophisticated adversaries and translating complex threat data into actionable intelligence. This is a hands-on role where your insights will directly influence our defensive posture and help eliminate threats before they manifest in the core of global AI infrastructure.

What You Will Be Doing:

You will serve as the intelligence core of our team dedicated to identifying, analyzing, and mitigating threats against our products and ecosystem:

Lead deep-dive OSINT and WEBINT research to identify emerging threats, conducting intelligence collection and analysis that leads to clear, actionable mitigation recommendations.
Leverage scripting (Python, Bash, etc.) and Generative AI tools to automate intelligence collection, triage, and analysis workflows.
Analyze Advanced Persistent Threats (APTs) and sophisticated adversaries, collaborating with multi-functional teams to detect, track, and eliminate potential risks to our networking portfolio.
Apply extensive insight into cyber operation phases to map adversary behavior, anticipate future movements, and harden our product development lifecycle with adoption of security improvements.
Drive threat hunting methodologies, proactively searching for indicators of compromise (IoCs) and hidden vulnerabilities within the products.
Translate complex technical findings into strategic intelligence reports for both technical collaborators and leadership, ensuring a clear and unified insight into the threat landscape.
Collaborate closely with incident response and engineering teams to ensure intelligence findings are seamlessly coordinated into other defensive tools and product security processes.

The Networking Application Engineering team is looking for a motivated, experienced Senior Hardware Engineer to join us in supporting groundbreaking network technologies. In this role, you will have a significant impact on both our business and the technology ecosystem, working closely with customers and R&D teams to shape the future of supercomputing and networking.

What youll be doing:

Support the integration of our latest Network Interface Cards (NICs) with major cloud providers.

Assist with the deployment of new supercomputer technologies and data centers.

Build and maintain customer trust by understanding and addressing their needs.

Collaborate closely with R&D teams to develop and refine features based on customer requirements.

Lead efforts to resolve complex and high-profile customer issues.

Provide constructive feedback to engineering and marketing teams regarding product requirements.

Our Networking Research group is seeking a forward-thinking Engineering Manager with a product leadership approach to manage a team of Software Engineers, AI Agent Developers, and Researchers.

In this role, you will bridge the gap between brand-new AI research and practical engineering. You will lead the charge in integrating autonomous AI agents into the daily workflows of our architects, hardware designers, and researchers. You will be responsible for understanding internal engineering bottlenecks, researching the latest academic and industry advancements, and translating them into deployed production tools using our AI stack.

What you'll be doing:

Team Leadership & Strategy: Lead and mentor a mixed team of SW engineers and researchers, balancing the agility of research with the responsibility of production software engineering.

Product Engineering: Partner with internal engineering teams (Hardware, Architecture, Research) to analyze their workflows, identify friction points, and architect Agentic AI solutions to accelerate their work.

Applied Research: Actively monitor the latest AI trends, academic papers, and technical blogs (LLMs, Agents, RAG). Translate these insights into concrete features and tools for the team.

Agent Architecture: Be responsible for the design of scalable frameworks for AI agent interaction, ensuring they can reason, plan, and orchestrate tasks within complex engineering environments.

SW-Focused MLOps: Define and implement the software lifecycle for AI models - from fine-tuning to deployment - utilizing our AI deployment tools and ensuring seamless CI/CD.

Production Deployment: Ensure reliable operation of agent fleets, optimizing for latency and resource consumption while maintaining security and access controls.

We are now looking for a Senior Chip Design RTL Design Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Plan and Design RTL units / blocks according to Arch & Micro arch specifications under challenging constraints with high orientation to power, area, and performance.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are now looking for a Senior Chip Design Verification Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:
Work in a combined design and verification team which develops some of the switch silicon core units.
Build reference models, verify and simulate chip blocks/entities according to specifications.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.

We are seeking an experienced technical leader to head our collective communication library development team. This role involves leading a team of engineers in developing high-performance collective communication implementations for multi-NPU and multi-node AI workloads.
Key Responsibilities
Lead the design and development of collective communication primitives (All-Reduce, All-to-All, Gather/Scatter and etc)
Architect scalable communication protocols for multi-NPU and multi-node systems
Optimize communication performance for NPU architectures
Provide technical leadership to the team members in NPU programming, distributed systems, and communication protocols
Work with a success-driven worldwide international team (Network, NPU, QA, AI, DL/ML Framework)
Define project milestones, deliverables, and technical roadmaps
Ensure compatibility with major AI frameworks (PyTorch, TensorFlow, JAX).

we are a global leader in hybrid control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software offer a groundbreaking approach to controlling quantum computers, scaling from individual qubits to arrays of thousands.
At the heart of our company is a passionate, ambitious team committed to transforming the construction and operation of quantum computers. Our deep understanding of customer needs drives us to deliver unmatched solutions in this revolutionary field.
We are looking for a highly experienced a hands-on Compiler Engineer who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
Responsibilities:
Develop our company's compiler from a proprietary quantum language to a proprietary processor tailored to realize and accelerate quantum computing.
Take on complex optimization challenges at the core of our unique compiler, focusing on real-time applications, hybrid quantum/classical algorithms, and parallel processing.
Conduct rigorous testing, debugging, and profiling to ensure the performance and correctness of compiler outputs.
Hands-on development and debugging of software to optimize the utilization of limited hardware resources, enabling the scaling of quantum computing systems and improving quantum algorithm performance on our cutting-edge quantum orchestration platform.
Collaborate closely with hardware, software and architecture teams to ensure seamless software-hardware integration, directly enhancing system capabilities and performance.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth, bringing about opportunities like those made possible with the invention of classical computing 50 years ago. At our company , we provide the worlds most leading researchers and organizations with the critical tools they need to develop useful quantum computers. our companys hardware and software represent a new paradigm for controlling quantum computers, from a single qubit to hundreds and thousands. We are assembling the strongest team of professionals in the world with the goal of revolutionizing how quantum computers are built and controlled and accelerating their arrival. we are backed by globally recognized venture capital sponsors, including TLV Partners, Battery Ventures, Red Dot Capital Partners, Avigdor Willenz investment group, Harel Insurance, and others.
We are looking for an excellent design engineer to join our team and build our company's state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Learning system and SW requirements for proper implementation of HW-SW interface
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation.

we are a global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of our company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Communicate and work with multi-disciplined and multi-site teams.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
The ML, Systems, & Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
Design and build tests to verify that the SoC design meets those targets.
Develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
Analyze problems, identify core design weaknesses, and drive the resolution of performance issues in both pre and post-silicon environments.
Develop performance measurement frameworks, including key performance indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making.