לוח משרות דרושים ASIC / VLSI בתל אביב יפו

We are seeking an experienced ASIC AI/ML Engineer with deep expertise in AI/ML infrastructure and application development specifically for semiconductor design verification disciplines. The ideal candidate will have a proven track record of delivering end-to-end AI solutions from concept to large-scale production deployment.
In this role, you will collaborate directly with architects, designers, verification engineers, software teams, and backend specialists to define best practices and deploy production-ready AI-driven workflows and applications. Your focus will be on implementing LLM, GenAI, and classical ML solutions that transform our ASIC design verification processes and accelerate our path to tape-out.
Key job responsibilities
Develop and maintain scalable AI/ML infrastructure for ASIC design and verification teams
Architect, develop, and deploy production-ready AI/ML applications for semiconductor design workflows
Design and implement GenAI solutions including LLMs and agentic AI systems for verification processes Invent innovative AI-driven solutions to eliminate identified inefficiencies in design and verification flows
Establish best practices and standards for AI/ML application development in semiconductor environments
Create monitoring and observability frameworks for AI model performance in production design environments
Collaborate cross-functionally with architects, designers, verification engineers, and software teams
Research and evaluate emerging AI technologies for applicability to semiconductor design challenges.

we are looking for a Experienced Verification Team Leader - FPGA/ASIC.
Lead verification for advanced ASIC/FPGA designs in a top-tier R&D team developing high-performance network interface solutions and customer-focused hardware.
Location: Tel Aviv office or our Beer Sheva office, which is located next to the train station.
Responsibilities:
Drive verification of complex, high-speed ASIC/FPGA designs
Define and implement advanced verification methodologies
Collaborate with architecture, software, and validation teams
Mentor engineers and promote technical excellence
Work with technologies like high-speed interfaces, network processors, and SoCs

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

We are at the forefront of AI-driven innovation in VLSI design automation. Join us to shape the future of semiconductor design with cutting-edge AI tools and make a significant impact in a collaborative, high-performance environment. Are you ready to push the boundaries of whats possible in VLSI CAD? Come be part of our pioneering team!

What you'll be doing:
You will be responsible for developing and integrating advanced CAD solutions and automation flows using AI and machine learning for VLSI design, verification, and implementation.
Work closely with design, verification, and CAD teams to identify areas for improving VLSI workflows using advanced tools and methods.
Research, prototype, and deploy AI-based algorithms.
Develop and maintain scripts and automation infrastructure to enable seamless adoption of AI tools in the VLSI design process.
Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date.
Provide technical support and training to engineering teams on AI-enabled CAD flows and best practices.

we are looking for a Physical Design Technical Leader.

we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

we are looking for a Senior CAD Engineer.
What you'll do
You'll be joining our Physical Design team within Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.
You will be the tech lead for CAD within the team, leveraging your extensive backend and physical design experience to drive the development, optimization, and innovation of CAD methodologies and tools, ensuring the highest quality and efficiency in our chip design flows from RTL to GDS.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.

we are looking for a ASIC Design Engineer.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab

We are driving innovation in automotive technology, developing solutions that power the next generation of vehicles. We are looking for a Junior Engineer who is eager to learn, grow, and make an impact in a dynamic and innovative environment. This is a unique opportunity to work alongside experienced professionals, gain hands-on experience, and contribute to projects at the forefront of automotive electronics. If you are passionate about technology, curious to explore new challenges, and excited to make a real difference, we are the place to develop your skills, innovate, and grow your career.
Why join us?
* Work on cutting-edge automotive projects.
* Learn from a talented and supportive team.
* Gain exposure to real-world automotive challenges.
* Grow your career in a collaborative and inspiring environment.
If youre ready to take the next step in your career and be part of something meaningful, wed love to meet you!
About The Position:
As a Junior ASIC Design Engineer, you will take part in the full lifecycle of advanced chips that power the next generation of vehicles. This is a hands-on, growth-oriented role where youll work closely with experienced ASIC engineers, gain exposure to real silicon, and build a strong foundation in chip design and verification. In this role, you will:
* Be part of a professional ASIC team working on cutting-edge automotive solutions.
* Support and learn from real emulation platforms used in production-grade designs.
* Contribute to RTL implementation and gain practical experience in design flows.
* Assist with verification and backend (BE) activities, learning industry best practices.
* Participate in silicon bring-up, seeing your work come to life on real hardware This position is ideal for curious engineers who want to learn fast, take ownership, and grow into a key contributor in the world of automotive semiconductor design.

we are seeking a motivated and detail-oriented Software Engineer to join our innovative VLSI Design Automation team. This group is responsible for building advanced VLSI CAD solutions and web-based platforms. We are looking for a full-stack engineer who is excited about handling large-scale data, enhancing web performance, and developing intuitive dashboards and applications. The ideal candidate brings solid backend experience, a strong data-driven mindset, a passion for learning, and excellent collaboration skills.
What youll be doing:
Design, develop, test, integrate CI/CD pipelines, deploy, and support features for web applications and dashboards.
Own the services and databases you build.
Identify areas for improving performance and inserting automation.