לוח משרות דרושים AI Engineer ברעננה

we are looking for a AI Automation Architect.
As AI Quality Architect, you are the person who makes quality native to the agentic SDLC.
You design the systems, standards, and intelligence layers that ensure every stage of an AI-accelerated pipeline - from requirement ingestion to autonomous deployment - is observable, trustworthy, and continuously improving.
You don't retrofit testing onto AI workflows; you architect quality into them from the ground up.

we are looking for a AI Quality Architect.
As AI Quality Architect, you are the person who makes quality native to the agentic SDLC. You design the systems, standards, and intelligence layers that ensure every stage of an AI-accelerated pipeline - from requirement ingestion to autonomous deployment - is observable, trustworthy, and continuously improving. You don't retrofit testing onto AI workflows; you architect quality into them from the ground up.

We are looking for a Senior Backend Engineer specialized in Generative AI to design agent workflows, optimize interactions with models (OpenAI, AWS Bedrock), and ensure the reliability of non-deterministic systems in production.

Tech Stack: Python (Asyncio), FastAPI, LangChain, LangGraph, Pydantic, Elasticsearch, AWS Bedrock / OpenAI API, LangSmith.

What You'll Do
Agent Architecture: Design and implement complex agent orchestration logic using LangGraph. You will define state management, conditional routing, and error handling within the agent graph.
Tool Engineering: Build and optimize the tool layer (function calling) that allows LLMs to interact with internal financial APIs and databases accurately.
Performance Optimization:
-Reduce end-to-end latency through asynchronous processing and streaming (SSE).
-Implement semantic caching strategies to minimize API costs and response time.
-Optimize token usage without sacrificing answer quality.
Observability & Evaluation: Implement automated evaluation pipelines using LangSmith. You will be responsible for setting up regression testing for prompts and agents to measure quality (correctness, faithfulness) before deployment.
Advanced RAG: Refine retrieval strategies. Work on hybrid search implementation (Keyword + Vector), re-ranking, and query expansion to feed the most relevant context to the model.

We are looking for a Senior HPC & AI Operation Engineer to join the Networking clusters solutions HPC/AI Infrastructure team. We are building supercomputers and AI clusters based on groundbreaking technologies. We are looking for a system administrator to be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and GPU computing
You will work with the latest Accelerated computing and Deep Learning software and hardware platforms, and with many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions. You will interact with HPC, OS, GPU compute, and systems specialist to architect, develop and bring up large scale performance platforms. Does this sound like you? If so, we would love to hear from you!
What you will be doing:
Deploy, manage and maintain large scale HPC/AI clusters
Managing Linux job/workload schedules and orchestration tools
Support and maintain continuous integration and delivery pipelines
Troubleshooting and fixing, bottom up from bare metal, operating system, software stack and application level
Supporting Research & Development activities and engaging in POCs/POVs for future improvements.

The AI Graph Compiler Engineer will design and develop next-generation graph compiler technologies enabling efficient execution of advanced AI models on our company Neural Processing Units (NPUs) used in edge and embedded AI devices. In this role, you will work at the intersection of AI frameworks, graph optimization, and hardware acceleration, enabling efficient execution of neural networks on cutting-edge AI hardware.
You will work at the intersection of AI frameworks, compiler infrastructure, and hardware acceleration, helping translate high-level AI models into highly optimized executions on our company NPUs.
What will you do:
Develop and enhance AI graph compiler components targeting our company NPU architectures. Implement graph-level optimizations such as operator fusion, scheduling, memory planning, and layout transformations. Participate in lowering models from AI frameworks (e.g., PyTorch, ONNX, TensorFlow) into our company NPU-optimized representations. Contribute to compiler passes focused on performance, memory efficiency, and numerical correctness. Collaborate closely with hardware, runtime, and AI framework teams to achieve optimal end-to-end performance. Analyze performance bottlenecks and assist in compiler-based optimizations. Debug and resolve issues across compiler, runtime, and hardware layers. Support testing, validation, and documentation of compiler features.

In this role, you will be a key contributor to the design and implementation of our companys AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.
You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of our company NPU embedded solutions, actively promoting our company AI capabilities to the customers.
What will you do:
Own and design key components of the AI Graph Compiler software stack for NPU-based systems.
Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.
Collaborate on HW-SW co-design, influencing NPU architecture.
Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.
Mentor junior engineers and contribute to technical best practices.

In this role, you will be a key contributor to the design and implementation of our companys AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.
You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of our companyNPU embedded solutions, actively promoting our company AI capabilities to the customers.
What will you do:
Own and design key components of the AI Graph Compiler software stack for NPU-based systems.
Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.
Collaborate on HW-SW co-design, influencing NPU architecture.
Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.
Mentor junior engineers and contribute to technical best practices.

In this role, you will be shaping the future of our companys AI software stack for Neural Processing Units (NPUs). You will lead software architecture, define performance-critical components, and enable efficient execution of advanced neural networks under tight power, memory, and latency constraints.
You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of our company NPU embedded solutions, actively promoting our company AI capabilities to the customers.
We are seeking a high-impact motivated Software Architect to join our team and help shape the future of our advanced neural network AI Software Toolchain over our companys AI computing processors.
Responsibilities
Lead Software Architecture specification and supervise design for the most advanced Software Toolchain handling state-of-the-art Neural Processing Unit operation.
Design and promote holistic software solutions incorporating various aspects of NPU handling: from network retraining, graph compiling and network inference execution on the embedded systems.
Collaborate proactively with Product, Architecture, VLSI and Software teams to promote software leadership over various markets and compute SoCs.
Explore and translate state-of-the-art neural network and AI applications requirements into software architecture flows, encompassing hardware, software, tools and other components.
Evaluate architecture proposals, internal and external IP features and provide influential and inspirational leadership across hardware and software to align all parties to a common vision of architecture & technology development.
Represent our company with high technical credibility in customer meetings, appropriately incorporating feedback.
Boost velocity of development teams by providing technical guidance and by constantly looking ahead to anticipate and resolve future challenges.
Conduct experiments, invent and drive development of supporting tools such as simulators, models, profilers, and other methods as required.
Engage with engineering leadership and product planning stakeholders to develop technology roadmap.

In this role, you will be a key contributor to the design and implementation of our companys Edge AI software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.
You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of our company NPU embedded solutions, actively promoting our company AI capabilities to the customers.
What will you do:
Own and design key components of the Edge AI software stack for NPU-based systems.
Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.
Collaborate on HW-SW co-design, influencing NPU architecture.
Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.
Mentor junior engineers and contribute to technical best practices.