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As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of Full chip, IP, and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

As a Construction Project Manager supporting the Israel market, youll be a key point of contact for project delivery, taking complex projects from initial concept through due diligence, design, construction, commissioning, and handover across sites in Israel, primarily in Herzliya, Haifa, and Jerusalem.

Youll own ambiguous challenges as they arise, drive cross-functional alignment, and help enforce quality, schedule, and cost controls. The ideal candidate is a proactive problem-solver who coordinates effectively with a diverse group of stakeholders - including leadership, internal R&D/engineering partners, architects and the Global Design Team, engineers, corporate procurement, global security, IT & AV teams, vendors, suppliers, and general contractors - to deliver functional, high-quality spaces on time and within budget.
Responsibilities
Scope & Strategy: Translate end-user and scientific requirements into actionable design criteria, defining project scope, milestones, and deliverables in partnership with key stakeholders. Use Apple devices, iOS, and internal software within Apples environment and network.
Planning & Procurement: Develop project execution plans (budgets, schedules, risk mitigation) and lead selection and management of architects, third-party PM and supervision firms, engineers, general contractors, and specialty trade vendors.
Design & Technical Integration: Oversee the design development process to preserve architectural intent while coordinating complex MEP and process utility systems critical to lab environments (e.g., HVAC, process piping/gases, clean dry air, tooling hookups, high-voltage capacity, UPS and generators).
Site Leadership & Craftsmanship: Serve as the on-site owners representative, monitoring work progress, identifying risks, and upholding standards for health, safety, schedule discipline, and finish quality befitting Apples high-design environments.
Project Controls & Financials: Manage project budgets, cost forecasting, contractor billing, and change orders, proactively flagging and addressing cost and schedule variances.
Permitting & Compliance: Lead local authority approvals, environmental health and safety requirements, and municipal permitting processes.
Handover & Operational Readiness: Coordinate transitions to facilities and end-users, including commissioning, punch lists, occupancy permits, and documentation handover (as-builts, warranties, O&M).

As a formal verification technical lead you'll work to identify targets and complete formal verification for single or multiple design blocks and IPs (CPU, Cellular and Connectivity IP, Audio and Image Processing IP, Neural Networks IP, Memory/DMA Controller, Security IP, Peripheral IP, Interconnects, Power management subsystems, etc.).

Responsibilities
You will be responsible for: Working with our world-classP design engineers to develop a formal micro-architecture specification. Formalizing the refinement from architecture to micro-architecture. Developing comprehensive formal verification test plan. Proving properties of the design, finding design bugs, and working closely with design teams to help improve the micro-architecture. Crafting novel and creative solutions for verifying complex design micro-architectures. Developing and implementing re-usable and optimized formal models and verification code base. Architecting correct-by-construction design methodologies for improved formal verification efficiency and productivity.