In this role, you can lead our teams to deliver fully functional "first silicon" IP designs, from defining initial constraints through high-quality tape-out. You will have the rare and rewarding privilege of crafting upcoming products that will delight and inspire millions of customers every single day.
Responsibilities
Own the entire IP-level netlist generation and timing convergence journey, from synthesis and UPF power intent to final sign-off.
Architect and manage complex timing constraints (SDC) for both standard and custom designs, ensuring sign-off quality from day one.
Drive Full Chip and block-level timing/noise convergence, including hierarchical timing flows and power optimizations.
Collaborate closely with RTL designers to understand clock architecture, DFT teams on mode constraints, and PNR teams to achieve flawless physical convergence.
Develop and support automated block and chip-level sign-off flows, working with CAD teams to shape cutting-edge methodologies that eliminate pessimism and accelerate convergence.
Perform deep-dive signal integrity (SI) and noise analysis, drive custom IP integration, and generate block-level budgets to ensure correlation with the Full Chip.
Requirements: B.Sc / M.Sc in Electrical Engineering.
5+ years of experience in the field, with at least 2-4 years specifically focused on ASIC timing constraints and Static Timing Analysis (STA).
Expertise in commercial STA tools (e.g., PrimeTime) and flow generation.
Deep understanding of the ASIC design flow, including hierarchical top-down design, timing closure, and backend sign-off.
Solid understanding of AC timing (from specs to implementation) and DFT modes.
Strong communication skills and a team-player mindset, with the ability to learn new flows and methods quickly.
This position is open to all candidates.