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we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII.

Key Responsibilities

Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs
Own the setup and validation of foundry technology files (e.g., StarRC/Quantus techfiles, TLU+, ITF) across various process corners
Perform correlation studies between different extraction tools and 3D field solvers (e.g., Raphael, QuickCap) to ensure modeling accuracy
Collaborate closely with the Signal Integrity (SI) and Power Integrity (PI) teams to provide accurate parasitic data for critical high-speed nets and power grids
Implement automated scripts (Tcl/Python) to streamline extraction regressions, data parsing, and PEX-to-STA (Static Timing Analysis) handoffs
Analyze the impact of layout effects (LDE) and parasitics on timing and power, providing feedback to the implementation team to optimize PPA
Interface with EDA vendors and foundries to resolve extraction tool bugs and methodology gaps related to advanced nodes (5nm/3nm)

we're seeking a highly skilled Physical Design Engineer specializing in EMIR & Power Integrity to join our local engineering powerhouse from the ground up.

This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon.

You will execute the Electro-Migration and IR Drop (EMIR) analysis and sign-off from block level to full-chip, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. You will be responsible for validating power grid architectures to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and yield of chips operating in the worlds most demanding AI and cloud environments.

Key Responsibilities

Execute static and dynamic IR drop analysis, signal/power electromigration (EM) verification, and self-heat analysis from the block level through to full-chip sign-off
Implement and maintain robust EMIR flows and methodologies using industry-standard tools (Ansys RedHawk-SC, Cadence Voltus, or equivalent)
Work with Physical Design teams to implement optimal power grid structures, via pillars, and strap distributions to minimize voltage drop while maximizing routing resources
Collaborate closely with Analog/SerDes designers to analyze current profiles and ensure robust power delivery to sensitive high-speed IP blocks
Partner with Package Design engineers to perform Chip-Package-System (CPS) co-analysis, optimizing bump patterns and package routing for superior Power Integrity
Perform root-cause analysis for voltage drop violations and EM risks, proposing and implementing layout fixes alongside the PD team
Verify current density rules for ESD protection networks and ensure compliance with strict foundry reliability constraints
Support silicon bring-up by correlating simulation results with actual silicon measurements and yield data

As a Staff Physical STA Expert , you will hold the keys to silicon success. You will be leading the STA activities end-to-end from Chip partition, Time budgeting through signoff of all the chips we develop. You will build and lead the STA team to run several chips signoffs in parallel. In addition, You will define the sign-off methodology for chips that power the worlds most advanced AI clusters. You will act as the central nervous system of the design process, bridging the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity.

Key Responsibilities

Take full ownership of the STA flow and sign-off methodologies. You will establish the rigorous criteria that ensure our products succeed in the most demanding data center environments
Collaborate closely with Architecture, Design, DFT, and Backend teams. You will lead timing reviews and work closely with block owners to navigate the path to sign-off convergence
Develop, optimize, and manage complex SDC constraints from the ground up, ensuring they are robust across multi-scenario environments
Tackle the challenges of cross-chip clock distribution networks and sophisticated margining techniques, ensuring robust silicon across all process corners
Have a passion for better workflows? Youll participate in design methodology improvements and tool automation, utilizing both industry-standard EDA tools and in-house automation to make our sign-off process faster and smarter

We are currently looking for a Performance Simulation Expert develop and evaluate next generation performance features as well as develop the future generation of our Compute system simulation infrastructure, models and analysis tools
Responsibilities:
Develop and analyze performance and power features in our cycle accurate pre-silicon model and improve the accuracy of the current Server system simulator
Design the architecture of the new generation system simulation platform that will be used to analyze performance of Server (Compute and AI) workloads and identify performance bottlenecks
Develop new technologies, methodologies and tools for simulation. Analysis and debug of applications and workload on Huawei servers
Propose and simulate optimizations and innovations on the HW and SW in order to improve server performance for given workloads
Distribute the simulation platform, train and support other teams in China and in Europe using the simulation platform, technology and methodology.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages
Potentially (in the future), lead a team doing above activities
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

Looking for a CPU Architect for codesign of HW/SW feature for our CPUs for cellphones and servers. The role includes but is not limited to:
Analysis of technical challenges and determination of whether to solve them by a combination of new HW and new SW or by only one of these
Invents corresponding HW features and SW solutions to address above challenges. Evaluates feasibility tradeoffs, explores, and defines new approaches and novel architectures for CPU. Develops the end-to-end architecture of new instructions (when applicable) in coordination with partners. Drives the inclusion of the feature in a CPU project working with micro-architects, designers and verification experts. (the HW/SW features are typically in the form of new instructions or of other Instruction Set constructs and belong to one of following domains: dense compute, general purpose accelerations, use case specific accelerations, system level instructions, Security related technologies, or instrumentation instructions.
Models CPU functionality, performance and power in simulators, analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usage.
Provides experimental/proof of concept changes for proposing design alternatives meeting performance, power, area, and timing constraints.
Reviews and influences cross functional roadmaps.
Collaborates with SW and HW architects, design, verification, and validation engineers during the execution of the project. Finds mitigations for issues that arise during implementation of his/her features.

Our goal is to design cutting-edge CPUs for smartphones, servers, and desktops, and we need the very best talent to help us achieve it!
The CPU Architect will take charge of defining a processor on chip inter-connect and coherent fabric that meets the requirement of high performance, high bandwidth, and scalable processing architecture. This architect will utilize his processor experience to deliver a world-class processor ASIC with many advanced features for Huawei products.

which department will you join?
our hw team - a group designing the eyeq chips for adas and autonomous cars. the group is responsible for all disciplines of development, including but not limited to logic design, design verification, microarchitecture, analog and circuit design and layout, physical and structural design ( backend ), product and TEST engineering.
each physical design engineer has an end to end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & rtl modifications to achieve converges were looking for a physical design engineer to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out. what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

which department will you join?
epg is a fast-paced, dynamic, and startup-like group responsible for researching, incubating and developing next-generation technologies and ideas, with a strong orientation towards computer vision, Machine Learning, data, and ai.
the group hosts a diverse team of scientists, engineers and developers to research, realize, and bring to market innovative new products, leveraging cutting-edge technologies, skills and capabilities.
were looking for a backend expert to join the growing physical design team, responsible for state of the art SOC design from definition to tape-out.
what will your job look like:
hands-on physical design block owner from rtl to gds.
floorplan exploration with guidance and collaboration with Front-End and architecture teams.
sta: work with fe and floor planner to manage block and top level constraints and 1st level of timing analysis.
synthesis exploration and final synthesis netlist: scan insertion @ synthesis, clean checks from lint, upf & spyglass.
place & route: from synthesis netlist to final layout and signoff verification with target to achieve best power performance and area.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
collaborate with architecture, design, and verification teams to develop new product bring-up, validation, characterization, and qualification strategies, manufacturing TEST solutions for new high performance computing (hpc) products in advanced process technologies.
verify TEST solutions on pre-silicon models (simulation or emulation) and develop ate TEST modules, dc tests, binning, production flows, and characterization flows.
develop and validate TEST programs on ate platforms for new product integration (npi) in preparation for high volume manufacturing (hvm), working with ate vendors.
support product sustainability, including volume data analysis of screening and characterization data, TEST time and yield improvements, TEST escapees and return merchandise authorizations (rmas) assessments, failure localization, containment measure implementation, and partnership with design manufacturing, quality, and reliability teams to root cause and implement corrective actions.
develop tools, flows, and methodologies to continuously improve and automate the testing.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.

you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.as a design & power methodology team manager within the server chip design team, you will be responsible of managing and leading design and power methodologies from ip to SOC, pre and post silicon. you will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.you will work closely with cad vendors and internal teams to develop lead design and power methodology and execution.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead flow and methodology development and assimilation across multiple groups. work closely with cad tool providers as well as internal cad teams.
plan, execute, track progress, assure quality, and report status.
work closely with internal customers and support multiple activities and deliverables.
drive design methodologies such as design construction, cdc, rdc, sdc. drive power at: ip and SOC rtl/gate level optimization, estimation, correlation.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will be part of a team developing application-specific integrated circuits (asics) used to accelerate networking in data centers. you will have multiple responsibilities in areas such as project definition, design, and implementation. you will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.you will also be responsible for performance analysis for a networking stack using your knowledge.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead an asic subsystem.
understand how it interacts with software and other asic subsystems to implement data center networks.
define hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and our cloud. our end users are , cloud customers and the billions of people who use our services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals.
design and build tests to verify that the SOC design meets those goals.
develop and implement advanced technologies for running benchmark representations on pre-silicon environments.
analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments.
develop performance measurement frameworks, including key performance indicators (kpis), to produce regular reports and dashboards that support stakeholder decision-making.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
lead an asic subsystem and understand how it interacts with software and other asic subsystems to implement groundbreaking data center networks.
define high-performance hardware/software interfaces. write micro architecture and design specifications.
define efficient micro-architecture and block partitioning/interfaces and flows.
implement designs in systemverilog.
collaborate with software, verification, and physical design stakeholders to ensure the designs are complete and correct.