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we are looking for a formal Verification engineer for our networking team!
this is an exciting opportunity to join a hardworking pre-silicon design and verification team, working on groundbreaking nic technologies. we deploy state-of-the art formal verification tools and methodologies to prove design correctness. working in our formal verification team will expose you to a wide range of cutting edge design and technologies. our nic team delivers world class cpu interface and offload solutions for hpc, data -center, network, and Storage markets. we micro-architect, verify, and deliver the best and most widely used high bw ethernet and ib nics in the industry. nvidia has the most sophisticated formal tools and methodologies in the industry, which help us achieve a0 design tapeouts. as part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
what you'll be doing:
in this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
you will work on ambitious designs along with our pre-silicon team and take part in developing the next generation of core technology.
learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

we are looking for a dft Verification engineer for developing the next generation dft technologies.
as a dft Verification engineer at our company, you will verify the design and implementation of our dft technologies in various projects. this position offers the opportunity to have real impact in a dynamic, technology-focused company impacting switches, nic and SOC product lines. we are working closely with a wide range of aspects - chip design, backend, verification and production testing. we are working on the most advanced technologies and complex products. our dft solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
what you'll be doing:
in this position, you will be responsible for verification of the dft design, architecture and micro-architecture using sophisticated verification methodologies.
as a member of our dft verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (testbenches, bfms, checkers, monitors), execute TEST /coverage plans, and verify the correctness of the design.
collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

our company is looking for an outstanding software Verification engineer to join the virtio-net verification team. you will closely work with our driver and sdk developers, performance team and gain a deep understanding of our networking products and technologies on top of our bluefield cards. you will lead features from design through implementation to integration into frameworks, develop robust infrastructure, and work collaboratively with cross-functional teams.
this position offers the opportunity to have a real impact in a dynamic, technology-focused company, influencing product lines that empower the most advanced data centers in the world. we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing.
what youll be doing:
work closely with virtio-net developers to TEST new components and features, including crafting and executing unit, functional, integration, and performance tests.
develop a verification environment that can qualify the product from functional and performance perspectives using Python.
analyze coverage measures to identify verification holes and to show progress towards product development and releases.
be responsible for the verification of system design and software using advanced verification methodologies.

looking for a motivated, experienced senior Hardware Engineer to join us in supporting groundbreaking network technologies. in this role, you will have a significant impact on both our business and the technology ecosystem, working closely with customers and r&d teams to shape the future of supercomputing and networking.
what youll be doing:
support the integration of our latest network interface cards (nics) with major cloud providers.
assist with the deployment of new supercomputer technologies and data centers.
build and maintain customer trust by understanding and addressing their needs.
collaborate closely with r&d teams to develop and refine features based on customer requirements.
lead efforts to resolve complex and high-profile customer issues.
provide constructive feedback to engineering and marketing teams regarding product requirements.

this senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. its a unique opportunity to shape our technology and empower customers to build the supercomputers and ai fabrics of tomorrow.
what you'll be doing: lead the architectural design, development, and optimization of cutting-edge pcie firmware, using ai-driven modeling and insights to deliver exceptional performance.
serve as a trusted technical expert by investigating, debugging, and resolving challenging pcie firmware issues for our most important customers.
collaborate closely with our chip design, verification, software, and Architecture Engineers to find root causes and develop robust, long-term solutions.
champion the integration of ai-assisted diagnostics and generative ai tools across the entire development lifecycle to boost team productivity and innovation.
translate customer needs and field data into actionable feedback that directly shapes the future of our products.

seeking an experienced software engineer to join the networking switch sw group, developing the switch operating system (nvos). key role in developing the nvos is critical for next-gen networking tech for hpc data centers. are you passionate about working on innovative technologies? then we want to hear from you!
what you'll be doing:
owning and leading the nvos including development, testing flow and product life cycle.
as a senior software engineer at nvidia, you will use your expertise in C ++ and Python to develop nvos features and support new products.
lead nvos integrations with fw, hardware, and production teams.
support internal and external customers for any nvos related items.

we are now looking for a motivated chip architect to use your creativity to work on the connectx network adapter with the highly inventive and knowledgeable team.
what you'll be doing:
define the network adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). work with related industry standards & customers on deploying your tech.
collaborate with teams across teams (physical design, logic design, system software, firmware, applications)
work on proof of concepts and advance development projects.
perform research and analysis for current and future architectures.
craft product design specifications.
serve as a focal point within the organization and distribute the knowledge that you acquire.

looking for an hpc and ai data center engineer to join the networking cloud solutions hpc/ai infrastructure team. we are focused on building supercomputers and hpc clusters based on groundbreaking technologies. we are looking for a lab manager, be a key player to the most exciting computing hardware and software to contribute to the latest breakthroughs in artificial intelligence and gpu computing. take part of building large-scale compute and deep learning software and hardware platforms, work together and support many scientific researchers, developers, and customers to craft improved workflows and develop new, leading differentiated solutions.
what you will be doing:
plan and build complex cluster and supercomputers in various of data center and labs
rack stack and cable management to ensure efficient use of space and easy maintenance
ensure data centers and labs power and cooling efficiency while optimizing rack space utilization
data centers and labs daily operation and support
installations for variety of infrastructure and solutions - cloud, vms, Storage, network, hpc and ai
perform troubleshooting - network, optic cabling, bare metal, operating system.
support research & development activities

our company is hiring a senior, hands-on engineer to lead technical innovation in our design verification (dv) automation infrastructure. this role requires a strong design/verification background combined with a proactive approach - identifying inefficiencies, proposing creative solutions, and implementing them with high ownership and impact. you will directly influence how verification is performed across our next-generation networking chips, enabling more scalable, efficient, and robust flows for complex asics powering the ai revolution. 
what you'll be doing:
lead the development of advanced verification automation tools, regression flows, and debug infrastructure.
identify key challenges and inefficiencies in current dv methodologies and proactively propose and implement improvements.
work closely with dv engineers, design teams, and tool developers to ensure solutions are practical and impactful.
balance innovation with hands-on engagement in daily dv issues - keeping a strong connection to real-world challenges and support needs.
act as a technical leader within the team, driving discussions, mentoring peers, and crafting strategic directions for dv automation.

we are hiring a skilled senior dpu performance Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and system -level performance root cause analysis.
what you will be doing:
learn and analyze system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die system simulations.
collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues.
develop and improve validation methodologies for performance experiments and data collection.
automate repetitive debug and validation tasks to scale coverage and efficiency.

Our Formal Verification (FV) team is seeking a visionary AI Verification Engineer to join our elite Networking Chip Design group. Our team is unique: we define the infrastructure and drive the methodologies for proving the correctness of the worlds most advanced AI and networking architectures. We operate at the cutting edge, leveraging a sophisticated ecosystem of proprietary in-house formal tools and industry-leading vendor EDA solutions.

In this role, you will be a key architect in our "AI-for-FV" evolution. You will work in close collaboration with our internal CAD and Design Technology AI teams to enhance our in-house toolset with artificial intelligence. You won't just be using tools; you will be building the "brains" that sit on top of them-utilizing LLMs and Machine Learning to automate intent-to-proof workflows and debug complex chips with unprecedented speed.

What Youll Be Doing:

In-House Tool Evolution: Partner closely with internal CAD teams to integrate AI capabilities directly into our proprietary FV infrastructure.

Methodology Architecture: Define and evolve the FV teams specialized methodologies, moving from manual property writing to AI-automated assertions.

Next-Gen Orchestration: Develop and integrate AI agents and ML models that interface with our toolchain to automate "intent-to-assertion" workflows and optimize coverage and convergence.

Intelligent Debugging: Create AI-based debug assistants that analyze formal counter-examples, categorize failures, and autonomously suggest fixes for complex logic problems.

Collaborative Intelligence: Act as the bridge between the FV team, Design Technology AI, and CAD groups to ensure our AI solutions provide end-to-end efficiency from RTL to A0 tapeout.

Leadership & Training: Act as the authority on AI integration, training the broader team on how to leverage "human-in-the-loop" AI tools and automated methodologies.

We are seeking a Principal verification engineer to be a technical lead in the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and adopting new technologies. One of our main goals is to define, build and use best in class technologies make sure that the chip design team works in an efficient manner and provides high-quality deliveries at scale. This position offers the opportunity to drive foundational flows and have a profound impact in a dynamic, technology-focused company.

What you'll be doing:

Define groundbreaking methodologies to create a flawless experience for verification engineers.

Mentor and guide designers and verification specialists to tackle complex technical challenges.

Identify design risks, define the verification scope, and lead infrastructure development to ensure design correctness.

Technically guide the development process of shared verification code and infrastructure to be widely used by the global chip design team.

Partner with the design automation team to provide end-to-end solutions that unify verification, simulation, and automation.

Collaborate with EDA vendors to learn about innovative tools/technology and integrate them into our long-term verification strategy.

Lead verification strategies, training sessions.

Join our DOCA Verification team as a Senior Software Verification Engineer and help shape the future of Data Processing Unit (DPU) and network interface cards software. We are seeking a highly motivated and skilled engineer with hands-on technical experience to verify the design and implementation of next-generation software features, with a focus on solving modern hyper scaler advanced networking aspect like congestion control and optimized network usage.

What you'll be doing:

Collaborate with software, architecture, product, and DevOps teams to define test requirements, coordinate releases, and deliver high-quality products.

Take end-to-end ownership of features: develop test plans, implement, and fully automate testing (primarily in Python).

Design, build, and maintain automated test scripts and frameworks.

Validate software functionality and performance through system-level and integration testing in Linux-based and virtualized environments.

Analyze test results, file bugs, track issues to closure, and ensure robust solutions.

Drive continuous improvement in verification flows and contribute to process and methodology enhancements.

Set up, maintain, and optimize test environments using Linux, Docker, and virtual machines.

Monitor nightly regression systems, analyze failures, and provide thorough root-cause analysis across hardware, OS, and software layers.