Required Digital IC Design- Intern
job requisition id
2604489
We are seeking a motivated and detail-oriented student to join our Design-for-Test (DFT) team as an ATPG (Automatic Test Pattern Generation) Engineer.
This role offers hands-on experience in the development and implementation of test methodologies for complex SoC designs, focusing on scan insertion, pattern generation, and fault coverage analysis.
Interact with IP teams/vendors to resolve all technical verification issues.
Work closely with design/DV/validation/SW teams
What You Can Expect:
Assist in scan insertion and ATPG flow setup for digital designs.
Generate and validate test patterns for stuck-at and transition faults.
Analyze fault coverage and identify areas for improvement.
Support silicon bring-up and debug of test-related issues.
Collaborate with design and verification teams to ensure testability requirements are met.
Document methodologies, results, and best practices.
Requirements: 2nd/3rd year Student for B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
Basic understanding of digital logic design and VLSI concepts.
Familiarity with scripting languages (e.g., Python, Perl, or TCL).
Exposure to EDA tools such as Synopsys TetraMAX, Cadence Modus, or similar is a plus.
Strong analytical and problem-solving skills.
Excellent communication and teamwork abilities.
This position is open to all candidates.