We are at the forefront of the AI revolution, delivering brand new accelerated compute platforms for global impact. Our Network Architecture group is seeking a talented and motivated Sr. Software Engineer to build the agentic workflows that our architects use in their daily work. The software at the center of this role is our hardware network simulation environment - you will design multi-step agent workflows over it, engineer the context that grounds them in our own specifications and source code, and optimize their runtime performance. If you are passionate about building the practical infrastructure that brings intelligent agents to life, we want to hear from you.


What you'll be doing:
Build agentic workflows - loops, graphs, and multi-step pipelines - that carry real hardware network simulation and analysis work end to end.
Engineer the context these workflows run on, turning our simulation models, specifications, design documents, and source code into context that makes agents accurate in our domain.
Work closely with network architects to understand their workflows and translate them into agent workflows they use daily.
Optimize the runtime performance of our simulation tooling on these platforms, including execution time, compute cost, and end-to-end latency.
Define evaluation and regression testing for agent workflows, so that changes to a prompt, a graph, or a context source are measurable.
Build observability across agent runs: what the agent did, where it failed, and why.
Champion guidelines for secure and reliable agent workflows, including data handling, access control, and interaction boundaries.
Serve as a key technical resource for solving sophisticated integration issues between agents and internal tooling.

We're looking for an AI researcher to take an integral part in research into how these models behave, how they should be evaluated, and how they can be deployed and used more efficiently across real engineering workloads.
This is a deeply technical research role with direct product impact.
You'll study frontier and open-source models, develop evaluation frameworks, investigate inference and model optimization techniques, explore local deployment strategies, and help answer questions such as:
Which model should handle a particular task?
How much capability do we lose when we quantize it?
Can a smaller local model replace a frontier API for a specific workload?
How should models be routed across latency, cost, privacy, and quality constraints?
How do we measure whether one model is actually better than another for agentic software engineering?
Your work will directly shape model strategy and the intelligence behind our AI infrastructure products.

Were looking for a Senior MLOps Engineer to be a core driver in how our product empowers security teams. You will be expected to deeply understand customer needs and translate them directly into product features that deliver real value. You'll own key parts of our frontend stack, drive key architectural decisions, and turn complex security data into clear, actionable business insights.

As we scale our AIDR product and expand deeper into model-driven security intelligence, we are looking for a Senior MLOps Engineer to own the infrastructure, tooling, and operational foundations that power our NLP and LLM training, evaluation, and deployment workflows.

You will architect and operate the systems that enable us to train, fine-tune, deploy, and monitor models at scale making our ML reliable, fast, cost-efficient, and production-ready.

This is a high-visibility, high-impact role where you will partner closely with DevOps, Backend, Data, and Product to establish world-class ML infrastructure from the ground up.

What Youll Do
Build & Scale ML Pipelines
Design, build, and maintain pipelines for training, fine-tuning, evaluating, and deploying NLP and LLM models across GPU and CPU environments.
Establish LLM-Focused CI/CD
Implement automated CI/CD workflows for ML models, including benchmarking, testing, performance gating, and production deployment.
Optimize Runtime & Inference
Select and optimize serving frameworks for low-latency, high-throughput inference, ensuring reliability and scalability.
Own ML Infrastructure
Manage training environments, experiment tracking, model registries, artifact versioning, and distributed training systems.
Operational Excellence
Monitor and optimize production models for performance, cost efficiency, availability, and observability.

Join our companys AI research group, a cross-functional team of ML engineers, researchers and security experts building the next generation of AI-powered security capabilities. Our mission is to leverage large language models to understand code, configuration, and human language at scale, and to turn this understanding into security AI capabilities which will drive our company AI future security solutions.
We foster a hands-on, research-driven culture where youll work with large-scale data, modern ML infrastructure, and a global product footprint that impacts over 100,000 organizations worldwide.
Key Responsibilities
Your Impact & Responsibilities
As a Senior ML Research Engineer, you will be responsible for the end-to-end lifecycle of large language models: from data definition and curation, through training and evaluation, to providing robust models that can be consumed by product and platform teams.
Own training and fine-tuning of LLMs / seq2seq models: Design and execute training pipelines for transformer-based models (encoder-decoder, decoder-only, retrievalaugmented, etc.), and fine-tune open-source LLMs on our company-specific data (security content, logs, incidents, customer interactions).
Apply advanced LLM training techniques such as instruction tuning, preference / contrastive learning, LoRA / PEFT, continual pre-training, and domain adaptation where appropriate.
Work deeply with data: define data strategies with product, research and domain experts; build and maintain data pipelines for collecting, cleaning, de-duplicating and labeling large-scale text, code and semi-structured data; and design synthetic data generation and augmentation pipelines.
Build robust evaluation and experimentation frameworks: define offline metrics for LLM quality (task-specific accuracy, calibration, hallucination rate, safety, latency and cost); implement automated evaluation suites (benchmarks, regression tests, redteaming scenarios); and track model performance over time.
Scale training and inference: use distributed training frameworks (e.g. DeepSpeed, FSDP, tensor/pipeline parallelism) to efficiently train models on multi-GPU / multi-node clusters, and optimize inference performance and cost with techniques such as quantization, distillation and caching.
Collaborate closely with security researchers and data engineers to turn domain knowledge and threat intelligence into high-value training and evaluation data, and to expose your models through well-defined interfaces to downstream product and platform teams.

We are is looking for a strong technical senior architect to join us in shaping the future. Senior Architects are innovators who can translate business needs into workable technology solutions. Their expertise is deep and broad. They are hands on, producing both detailed technical work and high-level architectural designs.

As a Senior architect in the AI Networking Research team, you will explore technological challenges on accelerate networking and building AI data centers. Research new transport functions and semantics for optimizing AI workloads, AI systems communication and accelerations and much more. You will also be leading architectural and development efforts across numerous technological fields, related to the modern AI data center, such as distributed AI and deep learning solutions, data analytics, High Performance Computing (HPC), Software Defined Networking (SDN), virtualization, storage, and more.

What youll be doing:

Enhance our GPU Networking offerings for accelerating AI workloads, such as our Dynamo, our NIXL and our UCX, tailored to the unique requirements of AI workloads.

Co-design hardware features (e.g., in GPUs, DPUs, or interconnects) that accelerate data movement and enable new capabilities for inference and model serving.

Identify and evaluate new technologies, innovations and partner relationships for alignment with our technology roadmap and business value.

Lead architecture and design of new technologies and innovations such as runtime systems, communication libraries, AI-specific technologies.

Lead proof-of-concept development to evaluate and drive such technologies.

We are seeking a highly skilled and versatile Performance Research and Analysis Manager to join our Performance Group. This role will drive end-to-end performance strategy and execution for our next-generation data centers and solutions based on GPU systems, NIC, Switch, DPU and Networking technologies. The ideal candidate will oversee, evaluating, and optimizing end-to-end AI GPU cluster-level performance for scaling out large scale distributed training and inference jobs communication. The role will focus heavily on RDMA, Networking Protocols, Collective Communication, Congestion Control, and Load Balancing algorithms. Secondarily, you will lead our DPUs and Storage technologies for N-S use cases to support AI Inference jobs. Third, you will drive our Performance Dashboards and Observability for cluster-level performance analysis from a stream line telemetry across NICs, Switches, GPUs, and NVlink.

What you'll be doing:

Drive end-to-end performance strategy, characterization, test plans, and optimization for our next-generation AI GPU clusters, focusing on large-scale distributed training and inference workloads.

Deeply evaluate and optimize our Networking core technologies performance, including RDMA/PRDMA, networking protocols, collective communication (NCCL), congestion control, and load-balancing algorithms.

Work on performance research and analysis of our DPUs and storage technologies in North-South (N-S) use cases and deployment scenarios to maximize performance and efficiency for AI inference jobs.

Drive the strategy for performance observability and dashboards across our next-generation data center solutions and supercomputers by leveraging scalable, streamlined telemetry pipelines to build performance dashboards and automated analytics based on real-time performance metrics across NICs, Switches, GPUs, and NVLink boundaries.

Perform deep root-cause analysis (RCA) on complex multi-node performance bottlenecks, driving actionable mitigation plans across hardware, firmware, and software teams.

Required ML Hardware Achitect
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will help shape the future of Clouds next-generation AI infrastructure, architecting high-performance Machine Learning silicon designed to power hyperscale AI inference. You will have an opportunity to drive accelerator technology that powers Generative AI models, large language models (LLMs), and emerging agentic workloads where throughput, latency, memory bandwidth, and energy efficiency are mission-critical.
You will be part of a silicon architecture team pushing the boundaries of custom computing. Leveraging your deep expertise in hardware-software co-design, machine learning algorithms, and computer architecture, you will define and optimize custom compute engines and memory hierarchies that accelerate the world's most advanced AI models across Cloud datacenters.
Responsibilities
Lead the architectural definition, modeling, and specification of next-generation, high-performance ML compute IP and acceleration blocks for Cloud AI silicon.
Own the ML IP architecture specification throughout the entire product lifecycle: concept exploration, cycle-accurate modeling, implementation, silicon bring-up, and production.
Partner closely with leading AI research and algorithm teams (e.g., Google DeepMind, Gemini research teams) and software compiler teams (XLA, PyTorch) to explore architectural trade-offs and define hardware requirements for emerging model architectures.
Drive comprehensive architecture studies, evaluating compute dataflows, numerical formats, sparsity, and specialized acceleration mechanisms such as key-value (KV) cache optimization.
Drive performance, latency, power efficiency, and silicon area projections across model topologies and workload configurations.

We are seeking an AI Networking Architect to join the Networking Research Group. This role bridges the gap between emerging AI workloads and the data center infrastructure that powers them, working at the intersection of AI applications, distributed systems, networking hardware, and software architecture. You will join a focused team of multidisciplinary engineers driving AI workload optimization through deep application understanding, network analysis, and end-to-end systems thinking. Your insights will directly shape our products across the full stack - from applications and software libraries to hardware architecture and physical design.


What you'll be doing:
Model the performance of complex AI workloads to identify bottlenecks and recommend system-level optimizations.
Analyze new AI models, distributed training techniques, and inference workloads to understand their infrastructure requirements.
Build simulation and hardware platforms, run real AI workloads on them, and develop analytical tools to evaluate trade-offs across compute, memory, storage, and network behavior.
Translate research insights and workload behavior into actionable software, xhardware, and networking architecture requirements.
Partner with architecture, software, and product teams to influence our future networking and AI infrastructure roadmaps.
Drive architectural innovation by applying deep workload analysis to production machine learning frameworks.

We're looking for our first Forward Deployed Engineer. You'll sit directly with our customers' engineering teams and get their workloads- from the first scoping conversation to a production endpoint carrying real traffic, at a cost and latency profile they couldn't hit anywhere else.
This is an engineering role. You will write code every day, in customer repos and in ours. It also carries pieces of solutions architecture, product management, and pre-sales, and you should want that mix rather than tolerate it. Ambiguous business goals come in; observable, benchmarked, production services go out.
As the founding FDE you also define the function: what a POC looks like, what we promise and measure, which patterns get productized, and how the field feeds the roadmap. The next FDEs will work from what you build here.
What You'll Do
Own customer outcomes end to end: problem framing, evaluation design, migration, deployment, benchmarking, monitoring. You're the technical owner from first call through expansion.
Win the POC: turn a vague objective into a tight spec and a working proof of concept fast, with explicit quality, latency, throughput, and cost-per-token targets - and hit them.
Tune serverless inference for real workloads: model and engine selection, batching strategy, KV cache behavior, speculative decoding, quantization, parallelism, cold-start and autoscaling behavior under bursty traffic. Diagnose regressions down to the inference engine.
Migrate workloads: move customers off OpenAI-compatible APIs, self-managed vLLM, SageMaker, or their own GPU fleets - and prove out the quality and cost delta with numbers.
Guide model strategy: advise on open-weight model selection, distillation, and fine-tuning for specific tasks; help customers get from a general-purpose frontier model to a smaller, faster, cheaper one that holds quality.
Close the product loop: bring the field back into the roadmap - write the PRDs, land the PRs, and turn one-off customer work into platform features.
Be the technical anchor in the room: support sales on complex evaluations, run technical onboarding, earn trust with staff engineers and CTOs.

We are building the first Neuron performance engineering team in Tel Aviv. As a Machine Learning Performance Engineer, you'll help shape the direction of this team from the ground up - profiling and optimizing workloads across the full ML software stack, writing high-performance kernels, and improving the Neuron SDK that external developers depend on. You'll work at the boundary between software and hardware, collaborating directly with compiler, runtime, and chip design engineers to close performance gaps customers care about.

The team is new and small, which means broad scope, direct ownership, and real influence over the technical direction we take. If you enjoy digging into performance bottlenecks and turning analysis into measurable wins, this role is for you.

Key job responsibilities
Design and implement high-performance compute kernels for ML operations, leveraging the Neuron architecture and programming models.
Profile ML workloads end-to-end to identify bottlenecks - memory, compute, or communication - and drive optimizations through to a measured improvement.
Enhance the programming model and tooling that kernel and model developers rely on, improving usability and debugging workflows.
Identify and drive optimization opportunities across the Neuron software stack (compiler, runtime, frameworks).
Document software designs, operational runbooks, and performance findings so the broader team can build on your work.

A day in the life
You might start your morning reviewing profiling data from a customer's large diffusion model training job, tracing a utilization gap back to a specific kernel. After a design discussion with compiler engineers about a new operator fusion strategy, you spend the afternoon writing and benchmarking a kernel prototype. Later, you review a teammate's pull request for a runtime optimization and share your findings in a short write-up for the broader Neuron organization. Your work directly translates into faster model execution and lower cost for AWS customers running ML workloads at scale.