דרושים » הנדסה » AI NPU VLSI Team Leader

In this role, as Senior Team Leader of the AI NPU Simulator, you will lead a Group developing a major part of AI simulation framework, in the core of our AI software offering. The AI NPU simulator enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company.

You will drive the development of robust, scalable, and efficient simulation software, working closely with global Architecture, VLSI, and Software teams to shape next generation of AI solutions.

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading software teams, and a track record of delivering complex, state-of-the-art products on time and with high quality. The ideal candidate is execution-driven, innovative, and passionate about building high-performing teams and cutting-edge AI technology.



Responsibilities

Manage and lead two teams (Development + Validation) .

Be accountable for the simulation lifecycle, including architecture, development, validation, and release.

Lead development of advanced simulation models for AI processors.

Own delivery of complex, multi-release roadmaps.

Ensure strong alignment between hardware design, compiler behavior, and simulation models.

Drive system-level correctness and performance accuracy.

Support system bring-up, debugging, and customer-facing activities when needed

We are looking for a CAD/Emulation Graduate Engineer to join our infrastructure team. This position is designed as an entry-level role for a recent graduate, providing hands-on experience with advanced VLSI CAD/Emulation and infrastructure



Key Responsibilities

Develop and maintain automation scripts for front-end Emulation and VLSI CAD flows and automation.

Support execution and releases of VLSI artifacts while marinating advanced CAD flows.

Assist in improving infrastructure efficiency and tool integration.

Work with version control systems and CI/CD pipelines for regression and build environments.

Own and rule top notch emulation methodologies and procedures.

Our HW team in Israel is looking for an experienced System Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:
CPO (Co Package Optic) Switch System architecture and design from concept to mass production.
Define the HW requirement, HW arch, board partition and lead electro-optic-mech concept. In addition - design/review HW aspects such as schematics, component selection, layout, opto-mechanics, DFM/T.
Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, Production, Software/Firmware, RTL and more.
The position consists of hands-on testing in lab environment for electrical and optical integration & validation, including problem solving while accompany production and qualification process.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.


What you'll be doing:

Implement chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design).

Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks.

Taking part in flows development and deployment.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, from supercomputers used in AI research to high-performance clusters used at almost every industry today, such as car and Pharmaceutical. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:

Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).

Research of various solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.

Developing models for simulations and performance testing, analysing the results and development of future HW and SW.

Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

We are looking for somone to join our WiFi hardware team.
Our team operates in an AI-driven environment where we leverage cutting-edge AI tools to enhance productivity, code quality, and reduce development timelines. You'll be expected to actively utilize and promote AI-assisted development practices within the team.
What you'll do:
In this role, you will work on defining, developing and debugging validation environments for TIs wireless MCU products targeted at Industrial markets. You'll Deep dive into both low level and system level modules, ensure compliance with specifications, collaborate with experienced software, Architecture, design and verification teams and build your skills through hands-on projects and dedicated mentorship.

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are looking for a Distinguished Engineer to help shape the future of AI infrastructure. As part of our advanced development and research efforts, you will drive technical vision and innovation across the AI software stack, spanning GPU computing, RDMA, NVLink, storage, and large-scale distributed systems. You will research next-generation system designs, influence product and platform direction, and help define how massive-scale AI environments are built, optimized, and operated through hardware-software co-design.

What youll be doing:

Research, define, and drive co-design solutions across AI software stacks involving GPU computing, RDMA networking, NVLink interconnects, storage, and large-scale distributed infrastructure.

Lead deep technical investigations and proof-of-concept development in areas related to distributed AI, deep learning systems, high-performance computing, virtualization, memory management, and large-scale systems design.

Work closely with multiple teams across us to advance next-generation AI infrastructure technologies and influence cross-stack co-design decisions.

Analyze end-to-end system bottlenecks and opportunities across compute, networking, memory, and storage layers to improve performance, scalability, and efficiency.

Guide the design of environments that support massive-scale AI training and inference workloads in production.

We are looking for an outstanding Senior Networking Software Architect to join the NIC/DPU Software and Firmware Architecture group. In this role, you will help define the next generation of our datacenter and AI networking platforms, with focus on DPU management, QoS, performance, telemetry, and software architecture across stacks. You will work closely with hardware designers, firmware/kernel driver teams, system engineers, validation, product management and customers. The role spans early architecture definition, pre-silicon design, bring-up, and production readiness for large-scale AI and cloud datacenter deployments.

What Youll Be Doing:

Own software and system architecture for next-generation DPU management, QoS, performance, telemetry, and observability features.

Define end-to-end control and management flows across DOCA, host drivers, embedded firmware, BMC, management controllers and external management systems.

Specify telemetry and observability requirements, including counters, logs, traces, events, health monitoring, debug data, and streaming telemetry.

Define management interfaces and APIs for configuration, provisioning, lifecycle operations, diagnostics, and field serviceability.

Write clear architecture specifications, interface definitions, flow diagrams, and design documents for software, firmware, and system teams.

Partner with R&D teams to translate high-level architecture into implementable designs and guide features through development, validation, silicon bring-up, and production.

Analyze system performance bottlenecks, interoperability issues, telemetry gaps, and customer-reported issues, then feed learnings into future architecture.

Collaborate with system and cluster architects to ensure NIC/DPU features fit end-to-end AI datacenter and cloud networking designs.

Required Staff GPU Verification Engineer
Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the world's most widely deployed GPU architecture - Mali. As a Staff Hardware Verification Engineer, you will play a key technical role in verifying advanced GPU components and subsystems, working alongside architects, designers and verification engineers to deliver high-quality, industry-leading graphics technology. You'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
Responsibilities:
Develop and execute verification plans for advanced GPU components and subsystems.
Develop and maintain AI tools, agents, and skills to support our engineering teams and workflows.
Build, maintain and enhance robust verification environments using SystemVerilog and UVM.
Apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
Debug complex functional issues and work closely with Design and Architecture teams to identify and resolve root causes.
Contribute to block-level and system-level verification, including environment integration and regression analysis.
Improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
Participate in verification reviews and support verification sign-off activities.
Share technical knowledge and collaborate with colleagues across the wider GPU engineering organisation.