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6 ימים
חברה חסויה
Location: Merkaz
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
BSc in Electronics Engineering or Computer Science
10+ Years of industry experience in verification, full chip dev. cycle.
Experience with System Verilog and UVM methodology - MUST
Advantages:
M.Sc. in Electronics Engineering or Computer Science
Working experience with Formal verification
Scripting skills in Python/Perl/shell
Hands-on experience with two or more of the following :
PCIE (Gen5 and above).
DDR (v4 and above).
AMBA protocol family, (inc. AXI4+, ACE/CHI)
ARM core architecture.
This position is open to all candidates.
 
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חברה חסויה
Location:
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
BSc in Electronics Engineering or Computer Science
10+ Years of industry experience in verification, full chip dev. cycle.
2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.)
Experience with System Verilog and UVM methodology - MUST
Advantages:
M.Sc. in Electronics Engineering or Computer Science
Working experience with Formal verification
Scripting skills in Python/Perl/shell
Hands-on experience with two or more of the following :
PCIE (Gen5 and above).
DDR (v4 and above).
AMBA protocol family, (inc.
This position is open to all candidates.
 
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09/08/2026
Location: Haifa
Job Type: Full Time
We are looking for engineers to join our Pre-Silicon Verification team - the team that sits at the very center of the chip development lifecycle.

As a CPU Verification Engineer on the Graviton team, you will be responsible for verifying the correctness, performance, and robustness of our next-generation ARM CPU cores and their surrounding subsystems. You'll work at the intersection of micro-architecture, system architecture, and software - ensuring our CPUs meet the highest quality bar before they reach silicon.
Requirements:
Basic Qualifications
- B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering degree.
- 5 years minimum experience in pre-silicon verification of complex digital designs.
- Working knowledge of ARM CPU architecture (ARMv8/ARMv9) privilege levels, exception model, memory model, and instruction set.
- Hands-on experience with SystemVerilog and UVM methodology.
- Experience with constrained-random verification, functional coverage, and assertions (SVA).

Preferred Qualifications
- Knowledge of the following programming languages (Python, Perl, shell).
- Knowledge of PCIe, Processors, Ethernet, DDR.
- Experience with formal verification tools and methodologies.
- Experience with performance modeling, profiling, or performance-driven verification.
- Experience verifying cache coherency mechanisms MOESI/MESI state machines, directory-based coherency, snoop filter operation, and multi-level cache hierarchies.
- Experience verifying ARM virtualization extensions.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We are looking for talented engineers to join the Pre-silicon Verification team and help us technically lead the challenges of the next decade, developing a semiconductor platform based on revolutionary architecture, and taking part in the development of cutting-edge products within a disruptive system architecture.

Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, and fast-paced environment.
Requirements:
Basic Qualifications
- Electrical/Computer Science engineer.
- 4+ years of experience with RTL verification.
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification),
- Sound understanding and knowledge of object-oriented programming concepts, Verilog/SystemVerilog/Specman.

Preferred Qualifications
- Knowledge of the following programming languages: Perl/Bash/TCl/Python.
- Knowledge of PCIe, Processors, Ethernet, DDR.
This position is open to all candidates.
 
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חברה חסויה
Location: Giv'atayim
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building a complex verification environment from scratch, and defining and executing a test plan. In this role, you will be leading verification from A to Z and will have a critical impact on the company.





Responsibilities
Review specifications and develop attributes, tests, and coverage plans
Define methodology and test benches
Work closely with the verification team to ensure the quality of the product
Build and maintain a smart and scalable verification environment that ties into various systems
Work with the software, design, and micro-architecture teams to understand the functional and performance goals of the products design
Requirements:
Requirements
6+ years of verification experience, including hands-on experience building complex environments from scratch
Advanced knowledge of verification flow, SOC architecture and design
Expertise in verification languages such as SystemVerilog, UVM, Spaceman
Knowledge of industry standard tools, including Verilog, Verilog simulator, and debug
Clear understanding of constrained random verification process, functional coverage, code coverage, and assertion methodology and philosophy
Bachelor degree in electrical engineering or computer science, or equivalent experience
This position is open to all candidates.
 
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Location: Haifa
Job Type: Full Time
We are looking for a Process Validation Engineer to join our Operations Engineering team and play a key role in ensuring the quality, compliance, and reliability of our manufacturing processes and equipment within a global medical device environment.

In this role, you will lead and support validation and risk management activities across internal and external operations, helping ensure compliance with FDA and ISO requirements while driving continuous improvement initiatives.
You will be responsible for managing validation programs, maintaining risk management documentation, supporting audits, and collaborating closely with cross-functional teams to ensure high standards across systems, products, and processes.

This position requires a strong combination of technical expertise, analytical thinking, organizational skills, and the ability to manage multiple priorities in a fast-paced and highly regulated environment.

Success in this role means becoming a trusted subject matter expert for validation and risk-related activities, driving projects forward with a high level of ownership, maintaining strong collaboration with internal and external stakeholders, and ensuring compliance and operational excellence across validation processes.

What you will do:
Lead the creation of high-level test plans, validation assessments, and validation plans, while overseeing execution progress and completion.
Review and approve test methods, validation test plans, and validation results.
Manage validation samples and support validation execution activities across internal and external operations.
Serve as a point of contact for subcontractor test laboratories and support coordination of validation-related activities.
Maintain and regularly update pFMEA documentation and related risk management records.
Identify risks, support mitigation planning, and implement actions to maintain compliance and process reliability.
Support and conduct internal audits according to the annual audit program and report audit findings.
Manage relevant Issues, NCMRs, and CAPAs related to validation and quality activities.
Serve as a Subject Matter Expert (SME) for validation activities during internal and external audits.
Support continuous improvement initiatives related to systems, products, services, and validation processes.
Participate in and support calibration and preventive maintenance programs for measuring devices and test equipment, as needed.
Requirements:
B.Sc. degree in a scientific discipline or related Engineering/Science field, preferably Electronics, or equivalent practical engineering qualification in a relevant field.
Minimum of 3 years of experience as a Quality Engineer in a multinational medical device manufacturing and distribution environment.
Experience with qualification and validation of test methods, manufacturing processes, and related equipment used in validation, verification, or manufacturing activities.
Strong knowledge and practical use of quality tools such as Six Sigma, statistical techniques, sampling principles, risk assessment, and root cause analysis.
Six Sigma certification - an advantage.
Experience planning and overseeing product validation studies within the pharma and/or medical device industry.
Working knowledge of FDA medical device Quality Systems Regulations and strong understanding of quality regulations and standards, including 21 CFR 820, ISO 13485, and MDR.
Understanding of electro-medical devices and relevant regulations - an advantage.
Excellent English communication skills, both written and verbal.
Strong organizational and analytical skills with close attention to detail.
Ability to manage multiple projects and priorities simultaneously while interfacing effectively across all organizational levels.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.

Responsibilities:
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Requirements
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.

Advantages
Knowledge in Low Power techniques and UPF standard.
Knowledge in Mix signals SoCs.
Experience with SW/HW Co-development
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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09/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Staff/ Principal Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
5+ years of proven experience in ASIC verification within the semiconductor industry
Hands-on experience developing components within complex verification environments using SystemVerilog
Strong working knowledge of standard verification methodologies, specifically UVM
Sharp analytical mind with passion for debugging and technical problem-solving
Excellent communication skills with ability to thrive in collaborative R&D environments
Preferred Qualifications
Master's degree in Electrical Engineering or related field
Familiarity with Formal Verification or Emulation flows
Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL
Experience with assertion-based verification and constrained-random testing
Background in connectivity or networking silicon verification.
This position is open to all candidates.
 
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10/08/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.
As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.
Key Responsibilities
Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified
Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process
Drive designs toward 100% verification closure through comprehensive test development
Contribute to verification methodology improvements and best practices
Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
Apply analytical skills and debugging techniques to solve intricate verification challenges
Collaborate effectively in a fast-paced, team-oriented R&D environment.
Requirements:
Bachelor's degree in Electrical Engineering or related technical field
3+ years of proven experience in ASIC verification within the semiconductor industry
Hands-on experience developing components within complex verification environments using SystemVerilog
Strong working knowledge of standard verification methodologies, specifically UVM
Sharp analytical mind with passion for debugging and technical problem-solving
Excellent communication skills with ability to thrive in collaborative R&D environments
Preferred Qualifications
Master's degree in Electrical Engineering or related field
Familiarity with Formal Verification or Emulation flows
Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL
Experience with assertion-based verification and constrained-random testing
Background in connectivity or networking silicon verification.
This position is open to all candidates.
 
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