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25/08/2026
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05/10/2026
חברה חסויה
Location:
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
BSc in Electronics Engineering or Computer Science

10+ Years of industry experience in verification, full chip dev. cycle.

2+ years of experience in leading a team of engineers (including technical and personal mentoring, etc.)

Experience with System Verilog and UVM methodology - MUST
This position is open to all candidates.
 
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05/10/2026
חברה חסויה
Location:
Job Type: Full Time
We are looking for highly motivated engineers who love the challenges and the opportunity of a small company. Join us and be a part of a small and dynamic team, which revolutionizes the parallel processor architecture.
Requirements:
BSc in Electronics Engineering or Computer Science

10+ Years of industry experience in verification, full chip dev. cycle.

Experience with System Verilog and UVM methodology - MUST
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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7 ימים
חברה חסויה
Location:
Job Type: Full Time
abra R&D is seeking a Verification Engineer. We are looking for a skilled Verification Engineer to join a professional and dynamic team and take part in advanced, diverse technology projects in the fields of FPGA Verification, signal processing, controllers, and more. This role requires extensive experience in Verification, UVM methodology, SystemVerilog, FPGA / ASIC verification environments, RTL debugging, simulation tools, scripting, and working closely with FPGA development, system, architecture, and algorithm teams. Key Responsibilities:
* Develop verification environments using UVM methodology for FPGA verification across various projects.
* Work on verification projects involving signal processing, controllers, and additional advanced technologies.
* Define, architect, and develop verification environments from block-level to full-chip level.
* Work closely with FPGA development teams, system engineers, architecture teams, and algorithm engineers.
* Support RTL debugging from block level to system level.
Requirements:
* B.Sc. in Electrical Engineering, Electronics Engineering, or Computer Science - an advantage.
* 3+ years of experience in Verification, from Test Plan definition through Coverage - mandatory.
* Hands-on experience with UVM methodology and SystemVerilog - mandatory.
* Experience developing Verification environments for FPGA / ASIC at both block and full-chip levels - mandatory.
* Experience with RTL debugging from block level to system level - mandatory.
* Experience working with simulation tools; Questa Simulator is an advantage
* Experience writing scripts in Python, TCL, Bash / Csh - mandatory.
* Experience working in a Linux environment - mandatory.
* Experience working with FPGA, architecture, system, and algorithm teams.
* Very good technical English. Personality requirements:
* Strong analytical and problem-solving skills.
* Ability to work independently and as part of a team.
* Ability to work in a multidisciplinary environment. A full-time on-site position based in Holon, Israel.
This position is open to all candidates.
 
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior DDR Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing. You will verify digital designs, collaborate closely with colleagues on projects, and perform direct validation. You will construct testbenches that exercise hardware through corner-cases and expose bugs. You will manage the full life-cycle from planning and execution to closing coverage.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
Experience with verification techniques, and the full verification life cycle.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with performance verification of ASICs and ASIC components.
Experience in DDR PHY/Controller verification activities.
Experience in DDR SoC integration and verification.
This position is open to all candidates.
 
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Location: Petah Tikva
Job Type: Full Time
we are a leading company specializing in the development and manufacturing of autonomous drone systems. Its solutions combine hardware, software, and AI-driven technologies to support complex, large-scale operations. our company works primarily with defense industries, such as military and law enforcement agencies worldwide. The company is part of Ondas Holdings and operates as a wholly owned subsidiary.
In this role, you will be part of the electronics engineering team responsible for leading projects end-to-end, including electronics design, drafting, design verification testing, collaboration with internal departments, external suppliers, and supporting development and production phases
Responsibilities
Planning, executing, and documenting verification & validation (V&V) tests for electronic circuits, assemblies, and multidisciplinary systems
Performing functional, electrical, environmental, and integration tests for airborne and ground electronic systems
Preparing, executing, and documenting ATP (Acceptance Test Procedure) and validation test documents
Operating laboratory equipment such as oscilloscopes, spectrum analyzers, signal generators, power supplies, multimeters, and data acquisition systems
Performing hands-on debugging and troubleshooting of electronic boards, communication interfaces, cables, and system-level failures
Supporting integration, bring-up, and verification activities throughout development and production stages
Writing detailed test reports, validation summaries, failure analyses, and technical documentation
Working closely with hardware, firmware, system engineering, integration, manufacturing, and production teams
Supporting qualification, acceptance, and reliability testing processes מול customers, subcontractors, and internal teams
Managing laboratory activities, maintaining test setups, and supporting calibration and organization of lab equipment
Solving technical and system-level challenges under tight schedules and multidisciplinary constraints.
Requirements:
Practical Engineer / B.Sc. in Electrical / Electronics Engineering from a recognized institution
5 years experience in electronic testing, validation, integration, or hardware verification
Hands-on experience with laboratory and electronic test equipment
Strong technical orientation and troubleshooting capabilities
Understanding of analog and digital electronic circuits
Ability to read schematics, wiring diagrams, and technical documentation
Ability to work independently and manage multiple tasks in parallel
Strong teamwork skills, interpersonal communication, organizational abilities, self-learning skills, and the ability to work under pressure
Advantages
Experience with airborne systems, drones, robotics, or multidisciplinary systems
Familiarity with environmental and qualification tests (EMI/EMC, vibration, thermal, etc.)
Experience with automated test systems and scripting tools (Python / LabVIEW / MATLAB)
Experience in production support and work with subcontractors
Experience with RF systems and communication equipment
Familiarity with communication protocols such as UART, SPI, I2C, CAN, and Ethernet
Experience writing and executing ATPs, test procedures, and technical reports.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Caesarea
Job Type: Full Time
In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.



Responsibilities:

Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
2+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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23/09/2026
Location: Haifa
Job Type: Full Time
We are looking for a Senior VLSI Verification Engineer to join the ride as we spearhead the next revolution in electronics!

Responsibilities
Develop and maintain advanced verification environments using SystemVerilog and UVM, ensuring scalability, configurability, and reusability across multiple IPs.
Design, implement, and execute comprehensive testbenches and random test suites to validate functional correctness, robustness, and corner-case behavior of complex IP within various SoC integration environments.
Drive coverage closure by defining, collecting, and analyzing code and functional coverage metrics; identify verification gaps and ensure complete validation of feature sets prior to sign-off.
Lead debug and root-cause analysis efforts in collaboration with senior verification and design engineers, leveraging carefully crafted logs, waveform analysis and assertions to isolate and resolve design or environment issues.
Collaborate closely with architecture, design, and firmware teams to ensure verification completeness, alignment with design intent, and seamless integration at the system level.
Contribute to methodology and infrastructure improvements, including reusable UVM components, automation scripts, and best practices that enhance team efficiency and verification quality.
Requirements:
Requirements:
B.Sc. in Electrical/Computer Engineering or equivalent.
5+ years of experience as a VLSI Verification Engineer. Expertise in System-Verilog and UVM.
Strong software development skills and the ability to develop reusable verification components and utilities.
Strong organizational and planning skills, with the ability to prioritize and drive verification projects to completion.
Effective communicator with a structured, detail-oriented approach to problem-solving and collaboration.

Advantages:
Experience with Git, Python, code templating methods, and open-source verification workflows.
Familiarity with full-chip level aspects of VLSI verification (reset architecture and sequences, power domains and modes, etc.).
Experience in firmware verification, including emulation-based verification on FPGA.
Experience with formal verification or mixed-signal simulation.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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24/09/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Senior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

Key Responsibilities

Verification Environment Development
Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks.
Develop and maintain System Verilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing.
Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified.

Coverage & Quality Assurance
Implement functional coverage models and analyze results to identify gaps in the verification process.
Drive designs toward 100% verification closure through comprehensive test development.
Contribute to verification methodology improvements and best practices.

Debug & Cross-Functional Collaboration
Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle.
Apply analytical skills and debugging techniques to solve intricate verification challenges.
Collaborate effectively in a fast-paced, team-oriented R&D environment.
Requirements:
Basic Qualifications
Bachelor's degree in Electrical Engineering or related technical field.
3+ years of proven experience in ASIC verification within the semiconductor industry.
Hands-on experience developing components within complex verification environments using System Verilog.
Strong working knowledge of standard verification methodologies, specifically UVM.
Sharp analytical mind with passion for debugging and technical problem-solving.
Excellent communication skills with ability to thrive in collaborative R&D environments.

Preferred Qualifications
Master's degree in Electrical Engineering or related field.
Familiarity with Formal Verification or Emulation flows.
Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks.
Exposure to industry-standard protocols such as AMBA, PCIe, Ethernet, or CXL.
Experience with assertion-based verification and constrained-random testing.
Background in connectivity or networking silicon verification.
This position is open to all candidates.
 
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Location: Haifa
Job Type: Full Time
We are looking for an Experienced Formal Verification Engineer to join a team of talented engineers developing next-generation silicon for autonomous driving platforms.
This is a unique opportunity to enter one of the most challenging and rewarding disciplines in hardware development. Formal Verification combines deep understanding of computer architecture, digital design, and advanced verification methodologies to prove hardware correctness and uncover bugs that traditional testing may never find.
What will your job look like:
Be the owner of formal verification environment from first draft to sign-off stage.
Apply formal methods to verify the correctness of various complex digital systems.
Work with HW architects\designers to define assumptions, rules and cover properties.
Help define the formal verification methodology and environment to be applied by the team.
Explore new Formal methods and Tools.
Work with tools like Cadence JasperGold, Verisium manager, Xcelium, Indago.
Analyze verification results, identify bugs, and collaborate with engineers to resolve design issues.
Develop generic formal blocks\functions of commonly used logic, to be later used off the shelf.
Requirements:
BSc in electrical engineering, computer engineering, or computer science.
Passion for the field of Formal Verification.
5+ years of experience in Formal Verification.
Experience coding system-verilog hardware description language.
Experience with scripting languages (e.g. python, tcl ).
Strong analytical and problem solving skills.
Ability to work independently and in a team-oriented environment.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Jerusalem
Job Type: Full Time
The Product Validation department is looking for a Validation Engineer.
Our department is responsible for delivering high-quality ADAS (Advanced Driver Assistance Systems) products.
We are the first line of support for our customers around the globe, and as our Validation Engineer, you will interact with most of our departments to achieve our goals.
What will your job look like:
Perform system-level validation of embedded systems, covering both hardware and software, with a strong focus on functional testing
Design and maintain test environments, including lab setups, test systems, and configurations.
Write and execute test plans and test cases based on system requirements, including manual and automated tests.
Validate communication protocols and system interfaces, and perform hardware bring-up and integration testing.
Install and support debug systems and sensors on development vehicles and assist automotive customers during integration.
Requirements:
B.Sc. in Electrical Engineering, Electronics Engineering, Communication Systems / Telecommunications Engineering, or equivalent.
At least 3 years of experience in validation, verification, or QA engineering.
Proven experience with embedded systems testing.
Experience working with communication protocols and basic networking concepts (e.g., data flows, interfaces, protocol behavior).
Hands-on experience with Linux-based systems.
Experience in test infrastructure, lab environments, and test setups.
Strong analytical, debugging, and problem-solving skills.
Strong teamwork abilities and excellent interpersonal communication skills.
Familiarity with defect tracking and validation tools (e.g., Jira) -an advantage.
Fluent in English and Hebrew.
This position is open to all candidates.
 
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