דרושים » תוכנה » Compilation Technology Expert

Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next-generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage, and networking at large scale. We aim to drive innovation and deliver software-defined infrastructure and algorithms for HPC, AI/ML, and Big Data applications.
We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.

What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software.
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU).
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale.
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations.
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads.
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions.
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally.
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction.
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data.
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models.
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages.
Potentially (in the future), lead a team doing above activities.
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for an individual contributor operating at the intersection of deep tech, the startup ecosystem, and academia, with strong technology analytical skills, clear communication, and a foundational background in computer architecture research.

In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups, and conducting technical due diligence.

Key Responsibilities
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.

We are looking for a junior Embedded Software Engineer, to join us in building the next generation of networking products. Youll have the opportunity to work on the technologies that power the worlds largest cloud provider, in a dynamic, open, fast-paced environment. Working for Annapurna Labs is thrilling and a constant learning experience. As an embedded SW development engineer, you will be responsible for developing features for Annapurna Labs next-generation hardware, to enable high network bandwidth and packets-per-seconds (PPS) performance, with consistently low latency. You will work to bring up a broad selection of instance types, optimized for various use cases, to suit each of our customers needs, such as varying combinations of CPU, memory, storage, and networking capabilities. As a SW development engineer, you will play a key role in shaping architecture definitions and SW system designs, and help to resolve complex customer issues. You will continuously evolve technically, while working to monitor AWS cloud health, maintain high quality standards, develop highly-optimized code, and provide exceptional customer satisfaction.

Key job responsibilities
We will be conducting a unique onboarding training program, where you will be studying the following with our technical experts and team leaders:
* Embedded systems basics.
* Annapurna technologies in EC2.
* Cloud compute development.
* Networking 101.

We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
* Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
* Supporting the Verification and Emulation teams: Test plan development, coverage review.
* Ensuring the chip meets quality and reliability standards.
* Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.

We are looking for a Principal Engineer with deep expertise in database internals, system architecture, and hardware-aware performance optimization.
This role is responsible for defining and driving advanced database performance solutions by understanding and improving the interaction between database engines, operating systems, and modern hardware architectures.
The ideal candidate is an experienced technical leader with a strong background in database systems, performance engineering, and computer architecture. The candidate should be capable of leading complex technical initiatives, influencing architectural decisions, and developing innovative solutions for next-generation database platforms.
This is a hands-on technical leadership role requiring expertise across database kernels, query execution, transaction processing, memory systems, and low-level performance optimization.

Responsibilities
Define and drive technical direction for database performance optimization and hardware-aware database architecture.
Lead the design and implementation of advanced database optimizations focused on scalability, efficiency, and workload performance.
Solve complex performance challenges across the full system stack, including database engines, query execution, transaction processing, concurrency control, storage engines, operating systems, and hardware platforms.
Design and develop optimizations leveraging modern hardware architectures, including multi-core CPUs, large-memory systems, NUMA platforms, CXL memory, RDMA networking, and advanced storage technologies.
Improve database execution engines, caching mechanisms, memory management, storage systems, and workload scheduling.
Analyze system behavior and identify bottlenecks using profiling, tracing, hardware performance counters, and low-level performance analysis.
Develop benchmarks, workload models, and methodologies to evaluate scalability, efficiency, and architectural tradeoffs.
Collaborate with database kernel, infrastructure, and engineering teams to influence architecture decisions and deliver high-impact improvements.
Mentor senior engineers and contribute to building technical expertise across the organization.
Drive innovation through research, prototyping, technical analysis, and architectural improvements.

*Part-Time or Full-Time Opportunity

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

As a leading technology innovator, we push the boundaries of what's possible to enable next-generation experiences and drive digital transformation, creating a smarter, connected future for all.

As a company AI Software Engineer, you will develop and implement cutting-edge AI techniques that enable the efficient utilization of state-of-the-art solutions across various technology verticals.

In this position, you will be responsible for leading software development and implementation of the company AI Stack features within our AI Runtime (QAIRT) SDK, specifically Core software including Generative AI Inference Extensions. You will contribute to the efficient execution of advanced deep neural networks (DNNs), large language models (LLMs), and other modern AI architectures. You will also be responsible for supporting AI stack that optimizes runtime efficiency, latency and power consumption of AI applications running Machine Learning workloads on our low-power AI accelerators. The DSP core design work directly supports our NPU and GPU solutions, enabling optimized inference across diverse hardware platforms.

You will have the opportunity to demonstrate your passion for software design and development through your analytical, design, programming, and debugging skills.
Responsibilities
Develop real-time software for our AI DSPs to support the execution of the latest generative AI models on Snapdragon platforms

Develop and implement core components of our AI Stack runtime framework for inference on resource constrained AI systems, operating in low power, small memory footprint platforms

Validate, analyze, and optimize the performance and accuracy of software through detailed testing of machine learning use cases

Debug complex issues, perform root cause analysis, and ensure high system reliability

Collaborate with cross-functional teams to deliver robust, scalable AI software solutions

Contribute to a culture of technical excellence, knowledge sharing, and continuous improvement within the AI Software team

Participate in design and code reviews

Working in global environment and collaborating inside the team and across other AI teams

Required Package Design/Layout Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of our AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Dive into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities. Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python and/or C/C++, running on Pre-Si emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues. Collaborate closely with architects, designers, and other teams to drive bug fixes and ensure feature functionality.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage. Mentor and guide junior engineers as the team grows.

We are looking for a Senior Network SW Engineer to join the SW group and take a major part in redefining the future of AWS cloud.
Were searching for engineers with a passion for networking to develop SRD (Scalable Reliable Datagram). SRD is a high-performance, low-latency transport protocol used within Amazon Web Services (AWS) infrastructure to optimize network performance. SRD powers several high-impact, cutting-edge products, including on-demand ML and HPC platforms leveraging EFA, next-generation storage services built on EBS, and the future of AWS network traffic.

Key job responsibilities
As a Senior Network Software Engineer on SRD team, your primary role will be to develop and optimize the implementation of SRD technology across AWS's network infrastructure. Your responsibilities will encompass designing, deploying, and maintaining SRD code-base, ensuring its reliability and scalability to accommodate the demands of various applications. An essential part of your role will involve conducting extensive network simulations to evaluate system performance under different conditions, enabling you to identify potential bottlenecks and inefficiencies. Using these simulations, you will troubleshoot network issues and implement robust solutions, leading to minimal data loss and latency. Leveraging your in-depth understanding of network protocols and AWS infrastructure, you'll refine and improve the SRD system's performance. Furthermore, you will be expected to mentor junior team members, leading projects to advance the SRD capabilities within the AWS environment. Staying updated with the latest industry trends and incorporating them into strategic network service planning.