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Our team at the Huawei Computing Network Innovation Lab is looking for exceptional talent to join us and lead the development of next-generation data centers. We create cutting-edge technologies that synergize software and hardware in tandem to accelerate compute, storage, and networking at large scale. We aim to drive innovation and deliver software-defined infrastructure and algorithms for HPC, AI/ML, and Big Data applications.
We are looking for an outstanding Research Team Lead with deep hands-on expertise in large-scale distributed systems, AI framework infrastructure, and performance optimization on custom accelerators. If you are a visionary technical leader, a skilled communicator, and a team builder who thrives at the frontier of systems and AI research - you're welcome on board.

What Will You Be Doing?
Lead and grow a world-class team of researchers and engineers working on distributed AI infrastructure and systems software.
Architect and own the software infrastructure enabling distributed training and inference on Huawei's custom accelerator hardware (e.g., Ascend NPU).
Drive research and development on communication libraries, runtime systems, memory management, and graph execution & synchronization at scale.
Optimize end-to-end performance across large-scale clusters, covering both scale-up (multi-device) and scale-out (multi-node) configurations.
Design and implement high-performance communication backends and collective operations (AllReduce, AllGather, broadcast) for distributed training workloads.
Collaborate cross-functionally with hardware architects, compiler teams, and framework engineers to co-design hardware-software solutions.
Publish and present research findings at top international venues (NeurIPS, EuroSys, SC, MLSys, OSDI) and represent the team externally.
Mentor engineers and researchers, conduct performance and growth reviews, and shape team culture and technical direction.
Partner with top academic institutions and open-source communities to advance the state of the art in distributed AI systems.

We are looking for a Principal Engineer with deep expertise in database internals, system architecture, and hardware-aware performance optimization.
This role is responsible for defining and driving advanced database performance solutions by understanding and improving the interaction between database engines, operating systems, and modern hardware architectures.
The ideal candidate is an experienced technical leader with a strong background in database systems, performance engineering, and computer architecture. The candidate should be capable of leading complex technical initiatives, influencing architectural decisions, and developing innovative solutions for next-generation database platforms.
This is a hands-on technical leadership role requiring expertise across database kernels, query execution, transaction processing, memory systems, and low-level performance optimization.

Responsibilities
Define and drive technical direction for database performance optimization and hardware-aware database architecture.
Lead the design and implementation of advanced database optimizations focused on scalability, efficiency, and workload performance.
Solve complex performance challenges across the full system stack, including database engines, query execution, transaction processing, concurrency control, storage engines, operating systems, and hardware platforms.
Design and develop optimizations leveraging modern hardware architectures, including multi-core CPUs, large-memory systems, NUMA platforms, CXL memory, RDMA networking, and advanced storage technologies.
Improve database execution engines, caching mechanisms, memory management, storage systems, and workload scheduling.
Analyze system behavior and identify bottlenecks using profiling, tracing, hardware performance counters, and low-level performance analysis.
Develop benchmarks, workload models, and methodologies to evaluate scalability, efficiency, and architectural tradeoffs.
Collaborate with database kernel, infrastructure, and engineering teams to influence architecture decisions and deliver high-impact improvements.
Mentor senior engineers and contribute to building technical expertise across the organization.
Drive innovation through research, prototyping, technical analysis, and architectural improvements.

*Part-Time or Full-Time Opportunity

In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.

Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system

We are forming a new team to explore AI Compilation Boundaries
This team will operate under a unique manner, as described below -
The environment
- Startup-like intensity
Small team
High ownership
High visibility
Merit is the essence, not titles
- Fast pace
Todays state of the art is tomorrows baseline
We aim to go beyond
- Incubator mindset
Take on hard challenges, dismantle, and regroup as novelty
- Elite technical culture
Strong experts
Strong standards
Strong execution.
Ratio beats seniority, not the other way around
- No artificial boundaries
We challenge assumptions, and question constraints, and leave no quarter
- Direct exposure to the latest and greatest AI technology
Real hardware
Real toolchains
Real large-scale AI applications
All pass through and impacted by our work
- First-principles thinking
out-of-the-box is a compromise
Do not accept that a box had to exist in the first place.

We are looking for an experienced Tech Lead to lead a team of 3-5 software engineers developing innovative database security and data protection solutions for enterprise platforms.

This is a hands-on technical leadership role focused on cybersecurity, data security, and advanced software engineering. The successful candidate will combine deep security expertise with strong software architecture skills to define technical direction, lead engineering execution, mentor developers, and build enterprise-grade security solutions.

The role requires strong technical ownership, the ability to solve complex security challenges, and close collaboration with security researchers, product teams, customers, and engineering organizations. Occasional travel may be required for technical discussions and customer engagements.

Responsibilities
Lead and mentor a team of 3-5 software engineers, providing technical guidance and driving engineering excellence.
Define software architecture, technical strategy, and development direction for database security products.
Design and develop advanced cybersecurity and data security solutions for enterprise environments.
Lead security architecture discussions, technical design reviews, and code reviews.
Translate complex security requirements and research concepts into practical, scalable software solutions.
Drive secure software development practices across architecture, design, implementation, and deployment.
Solve complex technical challenges related to security, reliability, scalability, and performance.
Collaborate with security researchers, product management, and cross-functional engineering teams.
Participate in customer-facing technical discussions and occasional international travel.
Remain hands-on and contribute to critical software components and technical decisions.

As HW Architect Team Leader, you will combine deep technical leadership with people leadership. You will shape next-generation networking silicon while building and mentoring a strong architecture team.

What Youll Be Doing
Lead, manage, and mentor a team of HW architects, fostering technical excellence and innovation.
Drive research, evaluation, and architectural definition of next-generation SoCs - from product requirements through production.
Define next-generation Packet Processor / Datapath / Congestion Management architectures for high-performance, complex SoC Ethernet and NIC switches.
Lead system architecture and detailed micro-architecture definition across major functional blocks.
Collaborate cross-functionally with design, verification, modeling, software, and other architecture teams to ensure end-to-end system alignment.
Identify and evaluate new technologies, methodologies, and architectural approaches for future products.
Provide technical direction, make key architectural trade-offs, and ensure execution excellence.

Looking for a CPU performance modeling architect to take responsibility over the performance aspects of new CPU instructions or modes of operation. The role includes but is not limited to:
Partners with lead SW and HW architects to co-invent optimal HW and SW solutions that come to address requirements. Influences the direction based on experiments and simulation data.
Models CPU functionality, performance and/or power in pre-silicon simulators
Defines and runs performance experiments to aid feature definition. Such experiments can be performed on a pre-silicon simulation environment or in a real system or on a combination of both or even in combination with analytical models.
Provides experimental/proof of concept for new features and implementation alternatives meeting performance constraints.
Analyzes the bottlenecks of current CPUs on workloads that reflect CPU future usages.
Potentially (in the future), lead a team doing above activities.
An adequately qualified candidate can also become the leader of definition for some features in addition to all the roles above.

We are seeking a seasoned Sr Staff Physical Design Engineer to provide technical leadership across full-chip and multi-die physical implementation on advanced TSMC FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

What You'll Do
Architect and own the full-chip physical design strategy: floorplanning, power delivery network (PDN), clock architecture, PnR, and timing closure
Define and drive backend methodology standards across the team for advanced node tapeouts (N5/N4P/N3)
Lead critical timing closure efforts - MCMM, OCV, advanced ECO strategies, and cross-corner sign-off
Oversee and guide signal integrity, power integrity, EM/IR, and reliability analysis for full-chip designs
Architect and lead the development of scalable PD flow infrastructure using Python and TCL - including automated regression, sign-off reporting, and run management systems
Champion the adoption of Agentic AI in the design flow - define use cases, evaluate tools, prototype autonomous agents for floorplan exploration, timing closure, and ECO automation
Lead cross-functional design reviews with DFT, verification, analog, and process engineering teams
Interface with TSMC, EDA vendors (Synopsys, Cadence, Siemens), and internal research teams to evaluate and adopt new methodologies
Mentor and technically guide junior and mid-level PD engineers across the organization

We are looking for an architect to work on the invention and development of new SW visible CPU technologies to improve performance of SW scenarios related to memory ordering, memory coherency, multithreading, synchronization, memory safety, caching, etc.
The minimal tasks of this role are:
1. Modeling of new memory related architectural features in the existing CPU performance simulator
2. Development of performance tests or adaptation of existing workloads to be suitable for simulation
3. Conducting performance studies for the workloads of choice either in the performance simulator or on a real chip
4. Develop analysis, conclusions and recommendations based on the above activities
The role can comprehend much more than that depending on the skills, talent and experience of the candidate creating a career path over time. For example, to invent new instructions and mechanisms to overcome significant performance bottlenecks in these areas, refinement and further development of ideas provided by others. Possible participation in development in additional domains
If you want to be part of something bigger, if you are a team player with excellent communication skills and motivation to revolutionize data-center technology, youre welcome on board!

As a leading technology innovator, we push the boundaries of what's possible to enable next-generation experiences and drive digital transformation, creating a smarter, connected future for all.

As a company AI Software Engineer, you will develop and implement cutting-edge AI techniques that enable the efficient utilization of state-of-the-art solutions across various technology verticals.

In this position, you will be responsible for leading software development and implementation of the company AI Stack features within our AI Runtime (QAIRT) SDK, specifically Core software including Generative AI Inference Extensions. You will contribute to the efficient execution of advanced deep neural networks (DNNs), large language models (LLMs), and other modern AI architectures. You will also be responsible for supporting AI stack that optimizes runtime efficiency, latency and power consumption of AI applications running Machine Learning workloads on our low-power AI accelerators. The DSP core design work directly supports our NPU and GPU solutions, enabling optimized inference across diverse hardware platforms.

You will have the opportunity to demonstrate your passion for software design and development through your analytical, design, programming, and debugging skills.
Responsibilities
Develop real-time software for our AI DSPs to support the execution of the latest generative AI models on Snapdragon platforms

Develop and implement core components of our AI Stack runtime framework for inference on resource constrained AI systems, operating in low power, small memory footprint platforms

Validate, analyze, and optimize the performance and accuracy of software through detailed testing of machine learning use cases

Debug complex issues, perform root cause analysis, and ensure high system reliability

Collaborate with cross-functional teams to deliver robust, scalable AI software solutions

Contribute to a culture of technical excellence, knowledge sharing, and continuous improvement within the AI Software team

Participate in design and code reviews

Working in global environment and collaborating inside the team and across other AI teams