Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design
In this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.
Responsibilities:
Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.
Investigate various aspects of system design, including:
Network-on-Chip design, further including Topology exploration, routing algorithms, and protocol/flow-control design to support high-throughput collective communication, low-latency synchronization, and efficient model/data parallelism
Expressing and Mapping LLM Parallelism to Wafer-Scale System that simplify LLM parallelism (e.g., tensor, pipeline, and data parallelism) and efficiently map training and inference workloads onto wafer-scale system.

As a Software Development Engineer in Test on our team, you will own the quality of Nitro card embedded software and firmware. You will design, develop, and maintain test automation for embedded systems and components, covering hardware interface verification, real-time firmware behavior validation, firmware update integrity, and fleet-scale deployment confidence. You will collaborate closely with firmware development teams to troubleshoot complex system-level problems at the hardware-software boundary and ensure timely delivery of high-quality Nitro card software to AWS Cloud solutions.

Key job responsibilities
- Own the firmware test automation framework - architect, develop, and extend a Python-based validation solution that scales across multiple Nitro card generations and hardware platforms, automating test coverage across the full firmware stack from boot sequences through board management layers and card-level system integration.
- Design and implement traceable, specification-driven test cases that validate firmware functional correctness, fault tolerance, and performance across hardware components, communication interfaces, and cross-subsystem interactions.
- Optimize CI/CD pipelines by integrating pre-merge and post-merge firmware validation, defining trigger policies per hardware generation, enforcing coding-standard compliance, and reducing commit-to-validated cycle time.
- Troubleshoot complex embedded system failures by analyzing firmware logs, system traces, and hardware diagnostics, then translate field incidents into targeted regression suites that prevent recurrence.
- Collaborate with firmware and hardware teams during new-generation silicon bring-up, define test plans, drive quality gates for production release, and mentor teammates on testing best practices and system architecture.

A day in the life
You start your morning reviewing overnight CI results and triaging any firmware validation failures flagged across active Nitro card generations. Mid-morning, you pair with a firmware engineer to debug a boot-sequence regression discovered during pre-merge testing, using hardware-in-the-loop test benches and system traces. After lunch, you join a design review for a next-generation Nitro card, providing input on testability and proposing validation strategies for new subsystem interfaces. Later, you refine your test framework to improve coverage for a recently released feature, then wrap up by sharing your findings in a team knowledge-sharing session.

Required SoC Chip Architect, Cloud, Silicon
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As an SoC Chip Architect, you will lead the definition of groundbreaking, high-performance custom silicon and multi-chiplet systems for our Cloud AI infrastructure. You will bridge the gap between hyperscale data center workload requirements and silicon implementation across various domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich SoCs.
You will be part of a team pushing the boundaries of custom silicon engineering, architecting next-generation data center products that deliver industry-leading performance, low latency, and massive bandwidth for Cloud and our flagship AI services.
Responsibilities
Lead top-level SoC architecture across multiple disciplines, including IP architects, digital design, verification, physical design, validation, firmware, power management, security, and system software.
Architect and analyze complex multi-chiplet systems, including chip partitioning, die-to-die (D2D) interconnects, advanced packaging constraints, and high-performance on-chip fabrics (NoC).
Define top-level SoC subsystems, memory hierarchies, clock distribution, reset schemes, and power domains to ensure optimal system performance and operational efficiency.
Formulate end-to-end operational flows, latency models, and system throughput analyses for data center workloads.
Own the SoC architecture specification and lead it throughout the complete product life-cycle: concept, modeling, implementation, tape-out, and post-silicon bring-up.

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, and decoupling capacitor placement.
- Perform RDL and substrate routing for high-density interconnects including microbumps, C4 bumps, TSVs, microvias, and PTH vias across multi-layer organic substrates or silicon interposers.
- Support die-level RDL routing and bump planning in coordination with ASIC physical design teams to help co-optimize the die-package interface.
- Contribute to cross-level layout co-optimization across die RDL, interposer/substrate, and PCB levels under guidance from senior engineers.
- Assist in maintaining package stack-up definitions in collaboration with SI/PI and materials engineering teams.
- Run physical verification checks (DRC, connectivity, shorts/opens) and support design closure.
- Follow and help refine package design rules and guidelines, working with OSAT partners and foundries to ensure DFM compliance.
- Collaborate with SI/PI engineers to incorporate electrical constraints into the physical layout - impedance-controlled routing, power plane optimization, and critical net shielding.

We are seeking an experienced Senior Real-Time Embedded Software Engineer to join our core engineering team and develop advanced software for high-performance, mission-critical embedded systems.

Key Responsibilities
Own tasks, infrastructure, and subsystems end-to-end, from requirements analysis and system modeling through design, implementation, testing, integration, and deployment.
Design, implement, integrate, and optimize real-time software for MCU-based platforms.
Translate system-level requirements into robust and efficient software solutions.
Lead software integration and validation on target platforms, including troubleshooting and system bring-up.
Contribute to the development and improvement of software infrastructure and platform-level capabilities.
Work closely with Hardware, Algorithms, and System Engineering teams within a multidisciplinary R&D environment.
Collaborate with relevant stakeholders to drive tasks and projects forward efficiently.

As member of the DV CAD team, you have the opportunity to impact our engineers who develop next generation of our products!
You will be responsible for developing software solutions used by thousands of DV engineers globally. You will be supporting design process of all chip families we make (iPhone, iPad, Mac, our Watch and more), and your work will help streamline this complex process. This role combines DV knowledge alongside modern software engineering practices. Your work will be very diverse, and you will have broad impact contributing to the success of us.


You will develop and drive software development of multiple tools across the DV space, including cloud-native services, GUI, LLM harness, CI/CD. Your work will span from software development and architecture to collaborating with DV engineers, working with EDA vendors, and supporting critical project milestones.

Responsibilities
Developing and maintaining LLM harness for agentic DV workflows, and being responsible for benchmarking and improving accuracy of agentic workflows.
Building and managing cloud-native services running on k8s, including CI/CD, containerization, alerting, databases, GUI and monitoring.
Communication with DV stakeholders and working to understand user requirements.
Writing and maintaining Python scripts used as part of design simulation flows.
Supporting multiple projects simultaneously.

Required Staff Design Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge.
Responsibilities
Lead an ASIC subsystem.
Understand how it interacts with software and other ASIC subsystems to implement data center networks.
Define hardware/software interfaces. Write micro architecture and design specifications.
Define efficient micro-architecture and block partitioning/interfaces and flows.
Collaborate closely with software, verification, and physical design stakeholders to ensure the designs are complete, correct, and performant.

we are looking for a Staff Systems Engineer.
As a Staff Systems Engineer, you will be a critical contributor on our Electrophysiology Systems Engineering team focused on delivering the future in Advanced Imaging. This role will involve a range of responsibilities including but not limited to collaborating and leading teams in the strategy, development and analysis of system architecture, system performance and system integration for our next generation products including various imaging modalities such as echocardiography, CT, MRI, and 3D cardiac mapping. In this role you will be a key member of product development team to bring systems from concept to launch.
Duties and Responsibilities:
Define and influence, and drive execution of technical strategy for system-level programs while partnering with cross-functional stakeholders on business strategy and product roadmaps.
Utilize multidisciplinary engineering knowledge and experience to design, develop, and troubleshoot new products specific to cardiac mapping and advanced imaging.
Provide system engineering leadership and take ownership for overall project success for new products and features from concept phase through launch.
Work with Product Marketing, Clinical Engineering, and Key Opinion Leaders to develop design input requirements from user and business needs.
Communicate with Sr. Management including technical presentations, status updates, and program reviews.
Lead project-level system architecture, system behavior definition, and tradeoff analysis activities utilizing Model-Based Systems Engineering (MBSE) methodologies, including use case modeling, requirements traceability, system architecture modeling, and interface definition.
Lead cross-functional working groups to solve complex problems, mitigate risks, and develop strategies to overcome challenges.
Plan, manage, and report on overall systems integration activities including root cause analysis and solution generation.
Identify, communicate, and proactively manage technical, integration, and program risks throughout the product development lifecycle.
Provide input into the technology and product roadmaps.
Be a strong team player and lead cross-functional teams to resolve issues and meet budget and schedule requirements.
Create a positive, collaborative culture amongst the technical teams while working to solve challenging engineering problems.
Mentor engineers across multiple disciplines and serve as a technical leader driving engineering excellence, sound systems thinking, and effective technical decision-making.
Ensure compliance with procedural and documentation requirements of , FDA, ISO and other regulatory bodies.

Required SoC Test Automation and Infrastructure Lead, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our data centers are the most advanced in the world. In this role, you will help to manufacture the SoCs that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high-volume manufacturing at wafer fabrications and Outsourced Semiconductor Assembly and Test (OSATs). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next-generation of chips.
You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices, drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs
You will have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
Responsibilities:
Provide tools, set the environment and create automation to silicon engineering (SiEng) teams, collaborate with Test, Product, quality and reliability (Q&R) and system-level test (SLT) teams.
Create smooth and effective ways to manage silicon engineering (SiEng) datastream to and from suppliers and internally, between different platforms, while optimizing formats and datalogs, convert per need.
Verify test solutions on pre-silicon models (simulation or emulation) and support Automated Test Equipment (ATE) test development setup and environment.
Develop test method for ATE platforms.
Provide pre and post silicon dashboards and indicators that will reflect the status, demonstrate progress and point on the gaps.

We are looking for a highly analytical, detail-oriented Innovation Expert to join our Open Innovation team. This role is ideal for candidates who sit at the intersection of deep tech, startup ecosystem and academy, possessing strong technology analytical skills, clear communication, and a foundational background in computer architecture research.
In this role, you will drive our external innovation strategy by managing academic research collaborations, scouting early-stage deep-tech startups and conducting technical due diligence.
Key Responsibilities:
Academic Cooperation & Research Partnerships: Identify and build direct collaboration agreements with world-class professors, research labs, and universities. Facilitate joint research projects, tech-transfer initiatives, and track academic spin-offs.
Startup Scouting & Ecosystem Mapping: Actively identify, source, and map early-stage deep-tech startups and emerging tech companies globally within the companys strategic domains.
Technical Due Diligence: Evaluate startup technologies, product-market fit, and team capabilities. Analyze technical validity and assess how external innovations align with our internal roadmaps.
Ecosystem Analysis: Conduct deep-dive analyses of startup ecosystems, venture capital trends, and academic spin-offs to identify high-potential investment and collaboration opportunities.
Investment & Collaboration Support: Synthesize technical and commercial findings into clear, structured scouting reports, investment tech memos, and presentations for senior leadership to drive partnership or investment decisions.
Cross-Border Collaboration: Act as a bridge between startup founders, academic innovators, and internal global teams (including European and China-based business units) to facilitate joint POCs, or investment reviews.
Track Tech Domains: AI infrastructure, advanced semiconductors, hardware-software co-design, and AI data movement.