דרושים » ניהול ביניים » Senior Digital Hardware Design Engineer

We are seeking a Senior RF Systems & Design Engineer to join our RF team and help architect and industrialize our next-generation Counter-UAS (C-UAS) multi-product hardware ecosystem. In this role, you will bridge the gap between high-level Software-Defined Radio (SDR) concepts and high-yield mass production. You will guide modular architectural layouts, define core interfaces for internal and external sensors, implement critical DFx methodologies, and mentor junior talent within an evolving, fast-paced technical landscape
Key Responsibilities
1. Architecture & System-Level Design
Architect modular, RF transceiver systems and define cascading link budgets (NF, Gain, IP3, P1dB) from antenna to converter.
Design advanced wideband SDR front-ends and direct RF sampling topologies tailored to defeat dynamic threats.
Establish Interface Control Documents (ICDs) and hardware abstraction standards to seamlessly integrate 3rd-party subsystems (Radar, EO/RF).
2. Detailed HW Design, Simulation & Validation
Lead schematic capture, high-frequency/high-density PCB layout supervision, and component choices (PAs, LNAs, synthesis filters).
Perform electromagnetic and circuit-level modeling (ADS, HFSS, or equivalent) to resolve structural EMI/EMC and co-site isolation issues.
Formulate strict engineering Verification & Validation (V&V) plans, overseeing environmental and compliance certifications.
3. DFx & Production Scale-Up
Champion Design for Manufacturing/Assembly/Test (DFM/DFA/DFT) workflows to ensure stable, repeatable high-yield production loops.
Define line-calibration algorithms, built-in self-tests (BIST), and leverage Statistical Process Control (SPC) data to reduce production and field escalations.
4. Leadership & Mentorship
Collaborate across disciplines (Mechanical, Digital, Cyber-Software) to systematically resolve thermal, power, and high-speed noise friction points.
Act as a primary technical mentor for junior engineers, implementing standard product lifecycle (PLC) gating and best practices.

we are seeking a highly motivated Power Integrity Engineer to join our Hardware Engineering team. In this role, you will be responsible for defining, analyzing, simulating, and validating power delivery networks (PDNs) for next-generation networking platforms supporting high-performance ASICs, advanced SerDes interfaces, optical modules, and AI-scale networking systems.
You will work closely with hardware architects, PCB designers, ASIC teams, signal integrity engineers, mechanical engineers, and manufacturing partners to ensure robust power delivery, optimal system performance, and successful product deployment.
Responsibilities:
Lead Power Integrity (PI) activities throughout the hardware development lifecycle, from architecture through production.
Define and optimize board-level and package-level Power Delivery Networks (PDNs) for high-current networking ASICs and supporting devices.
Perform pre-layout and post-layout PI simulations using industry-standard tools.
Establish target impedance requirements and validate compliance across all power rails.
Analyze DC voltage drop, AC impedance, transient response, and power distribution performance.
Collaborate with PCB layout engineers to optimize stackups, plane structures, decoupling strategies, and power routing.
Work closely with Signal Integrity engineers to ensure SI/PI co-optimization of high-speed interfaces.
Develop power integrity design guidelines and best practices for next-generation networking products.
Support schematic reviews, layout reviews, and design sign-off activities.
Perform laboratory measurements and correlation using oscilloscopes, VNAs, power analyzers, current probes, and related equipment.
Investigate and resolve PI-related issues during board bring-up, validation, and production.
Collaborate with ASIC, FPGA, memory, optics, and power component vendors to optimize overall system performance.
Drive continuous improvement of PI methodologies, simulation flows, and validation processes.

We are seeking a high-caliber, multidisciplinary Hardware Systems Architect & Tech Lead to serve as the technical cornerstone of our hardware development and system integration.
In this role, you will bridge high-level system requirements with physical deployment reality, acting as the designated "Tech Lead" driving day-to-day engineering execution.
This role demands a "System of Systems" mindset. Beyond engineering our core SDR and RF hardware architectures, you will orchestrate the physical, logical, and electrical integration of complex tactical sensor suites - incorporating software-defined radios, active/passive radar arrays, electro-optical (EO/IR) cameras, and jamming payloads.
You will steer the hardware through its entire lifecycle (PLCM) while implementing flawless Design for Excellence (DFx) frameworks.
KEY RESPONSIBILITIES:
System of Systems Integration: Architect, model, and define hardware-level interfaces and high-speed data flow paths for multi-sensor integration (SDR, Active/Passive Radar, EO/IR Cameras, and RF Jamming payloads).
Requirements Definition: Translate high-level operational and product demands into detailed, actionable hardware and system-level requirements, Interface Control Documents (ICDs), and structural specifications.
System Modeling: Establish and manage rigorous physical power, thermal, high-speed data bandwidth, and RF link budgets for deeply integrated tactical configurations.
Technical Ownership: Direct day-to-day engineering activities, lead comprehensive design reviews, and serve as the final authority on architectural and hardware design trade-offs.
Product Lifecycle Management (PLCM): Guide hardware products smoothly through the entire lifecycle-from early concept and prototyping to mass production, validation, field deployment, and subsequent obsolescence management.
Cross-Functional Orchestration: Align and coordinate specialized teams across RF/Analog, high-speed digital, FPGA, embedded software, and mechanical engineering to achieve seamless hardware/software synergy.
Test Strategy Definition: Architect and define the end-to-end testing, verification, and validation (V&V) strategy for complex hardware-software systems.
Progressive Integration: Design and oversee methodical integration plans, successfully migrating subsystems from standalone bench testing to full "System of Systems" integration.
System Verification: Oversee high-reliability Hardware-in-the-Loop (HIL) testing, RF performance verification, and automated test regression setups.
Operational Validation: Partner with field testing and QA teams to design real-world tactical validation scenarios (including drone flight trials and complex RF interference environments) to ensure top performance in the field.
DFx Implementation: Drive critical design decisions optimizing for manufacturability (DFM), automated testing (DFT), reliability (DFR), and target cost (DFC) without sacrificing tactical performance.

We are looking for a motivated Hardware Engineer to join our Hardware team in Raanana.

You will have the chance to develop your own skills in a flexible and energetic work atmosphere with friendly and experienced colleagues. You will have helpful supervision, opportunity to learn, modern tools and flexible work culture.

If you want to be a part of our growing company that is driven by innovation and is focused on building a future together with our employees, consider applying.

Principle duties and responsibilities:

Design hardware modules, subsystems and systems for synchronization products.

Develop schematics and guide PCB layout (high-speed, mixed-signal, power).

Select and evaluate components (ICs, power devices, oscillators, interfaces).

Design high-speed interfaces (e.g., 10G/25G Ethernet) with signal integrity considerations.

Contribute to hardware design specifications (HDS) and documentation.

Support system-level integration (HW, FPGA, SW).

Define and execute validation and integration test plans.

Debug complex board and system-level issues (mixed-signal, high-speed).

Perform lab bring-up, measurements, and performance characterization.

Support product transfer to manufacturing (NPI).

Collaborate with manufacturing and test teams for production readiness.

Investigate and resolve issues during production and field operation.

Ensure product reliability, quality, and compliance with applicable standards.

Functional Collaboration.

Work closely with FPGA, software, system, SIT/SVT and mechanical teams.

Participate in design reviews and technical discussions.

Interface with suppliers and external partners as required.

Evaluate and introduce new technologies and components.

Drive improvements in performance, power efficiency, and cost.

Contribute to system architecture discussions and design trade-offs.

Our HW team in Israel is looking for an experienced System Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity.

What you'll be doing:
CPO (Co Package Optic) Switch System architecture and design from concept to mass production.
Define the HW requirement, HW arch, board partition and lead electro-optic-mech concept. In addition - design/review HW aspects such as schematics, component selection, layout, opto-mechanics, DFM/T.
Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, Production, Software/Firmware, RTL and more.
The position consists of hands-on testing in lab environment for electrical and optical integration & validation, including problem solving while accompany production and qualification process.

Required RF/HW & System Validation Engineer
Scope:
As an RF/HW Validation Engineer, you will bridge the gap between HW/RF validation and complex system-level testing. You will design, develop, and execute automated and manual test plans to verify the performance, reliability, and compliance of our SDR (Software Defined Radio) architectures and multi-layered tactical systems (including integration with other systems).
Key Responsibilities:
System-Level Testing: Execute end-to-end system testing of counter-drone platforms, verifying the integration of RF hardware, firmware, and complex software-defined radio algorithms under real-world scenarios.
Hardware Product Testing: Test and validate various HW products, including antennas, radar systems, jammers, and related peripherals.
Failure Analysis & Troubleshooting: Debug complex RF anomalies, signal integrity issues, and system bugs down to the component/board level, working closely with RF Design, Board Design, and SW teams.
Documentation: Create comprehensive test plans (ATP/DTP), write test reports, and present data-driven analysis to cross-functional R&D teams to impact the next generation of hardware.

We are seeking a Senior System Management Architect to lead the management architecture for our advanced SmartNIC cards. You will be the resident expert for SmartNIC system management, ensuring that NIC ASICs, Baseboard Management Controllers (BMCs), MCUs, CPUs, and CPLDs operate in perfect unison. You will own the lifecycle management specifications for SmartNIC platforms-from factory provisioning and day-one deployment to complex orchestrated reset flows and secure recovery. If you are someone who enjoys looking at a high-level system diagram and then immediately diving into the I2C/I3C bus topologies and PLDM command structures required to make it work, this role is for you.

What you'll be doing:

System Architecture & Flow Definition: Define and document comprehensive production, provisioning, update, recovery and reset flows for SmartNIC cards. Crucially, you will ensure that these board-level architectural decisions perfectly align with and support overarching platform-level needs, orchestrating seamless coordination between the NIC ASIC, BMC, CPU, and peripheral components.

Security & Provisioning: Specify security provisioning flows including OTP fusing, secure boot enablement, attestation key injection, certificate chain management, RPMC key derivation, and PQC (Post-Quantum Cryptography) requirements. Define IPN-to-OPN transition and component locking procedures.

Protocol Implementation & Guidance: Specify the use of standard management protocols (MCTP, PLDM, SPDM, NC-SI) across internal board interfaces to achieve secure boot, firmware updates, and telemetry gathering.

Hardware/Software Intersect: Dive deep into device-level hardware and software behaviour. Define CPLD logic requirements, power-sequencing dependencies, and reset orchestration (e.g., handling PCIe PERST#, SBR, and forced resets) for multi-host and standalone SmartNIC environments.

Interface Management: Architect intra-board communication pathways using PCIe, I2C/I3C, USB, and SPI, ensuring robust out-of-band (OOB) and in-band management connectivity.

Cross-Functional Leadership: Collaborate tightly with Production teams, Hardware and Firmware Engineering, NIC FW/Driver teams, and QA to translate your architectural specifications into implementable, testable realities.

Technical Documentation: Author rigorous technical specifications, test plans, and architectural design documents to guide both development and factory production.

Our HW team designs innovative end-to-end connectivity solutions for GPU servers. Our products optimize data center performance and deliver industry-leading bandwidth and scalability. Our products are focused on delivering the most optimized power - performance communication solutions for industries like AI, ML, Cloud, Media and Entertainment as well as any other industry that can benefit from our Datastream acceleration.



What you'll be doing:

Lead Pioneering Switch System design from concept to mass production.

Collaborate and integrate with all HW project fields: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more.

Project decision maker - Technical focal point.

The position consists of product specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes.

In this role, as Senior Team Leader of the AI NPU Simulator, you will lead a Group developing a major part of AI simulation framework, in the core of our AI software offering. The AI NPU simulator enables the execution of state-of-the-art LLMs, Generative AI models, and neural networks with exceptional performance, impacting multiple hardware and software teams across the company.

You will drive the development of robust, scalable, and efficient simulation software, working closely with global Architecture, VLSI, and Software teams to shape next generation of AI solutions.

We are looking for an exceptional hands-on leader with strong technical expertise, proven experience leading software teams, and a track record of delivering complex, state-of-the-art products on time and with high quality. The ideal candidate is execution-driven, innovative, and passionate about building high-performing teams and cutting-edge AI technology.



Responsibilities

Manage and lead two teams (Development + Validation) .

Be accountable for the simulation lifecycle, including architecture, development, validation, and release.

Lead development of advanced simulation models for AI processors.

Own delivery of complex, multi-release roadmaps.

Ensure strong alignment between hardware design, compiler behavior, and simulation models.

Drive system-level correctness and performance accuracy.

Support system bring-up, debugging, and customer-facing activities when needed

Required Staff GPU Verification Engineer
Join our GPU Hardware Verification team in Raanana, Israel, and help shape the future of the world's most widely deployed GPU architecture - Mali. As a Staff Hardware Verification Engineer, you will play a key technical role in verifying advanced GPU components and subsystems, working alongside architects, designers and verification engineers to deliver high-quality, industry-leading graphics technology. You'll contribute to complex verification environments, solve challenging technical problems and help drive continuous improvements to our verification methodologies and flows.
Responsibilities:
Develop and execute verification plans for advanced GPU components and subsystems.
Develop and maintain AI tools, agents, and skills to support our engineering teams and workflows.
Build, maintain and enhance robust verification environments using SystemVerilog and UVM.
Apply coverage-driven, constrained-random and, where appropriate, formal verification techniques to achieve comprehensive functional coverage.
Debug complex functional issues and work closely with Design and Architecture teams to identify and resolve root causes.
Contribute to block-level and system-level verification, including environment integration and regression analysis.
Improve verification methodologies, automation, scripting and continuous integration flows to increase quality and efficiency.
Participate in verification reviews and support verification sign-off activities.
Share technical knowledge and collaborate with colleagues across the wider GPU engineering organisation.