דרושים » חשמל ואלקטרוניקה » מנהל /ת פרויקטים - מתח גבוה

We are looking for a RF System Director to join our R&D site.

You will report to the CTO of the Broadband Business Unit.


Location

On-site role - working daily from our offices in Caesarea

What you will be doing:

Own end to end RF system definition, from early requirements gathering through architecture, detailed specifications, and technical tradeoff analysis.
Lead RF technical strategy for current and future products, ensuring alignment with product, system, and business goals.
Drive proof of concept activities, feasibility studies, and risk reduction for new technologies and architectures.
Be deeply involved in detailed RF design, simulations, reviews, and hands-on technical decision making.
Be involved in prototyping, bring-up, DVT, regulatory and environmental qualifications, and design transfer to production.
Ensure high quality technical documentation across all phases of development, including specifications, design documents, test plans, and reports.
Work closely with cross-functional teams including digital, system, mechanical, manufacturing, QA, support, product management, sales, marketing, and key customers.
Support customer engagements, escalations, and field issues by providing deep RF expertise and root cause analysis.
Participate in technology roadmap planning and contribute to long term innovation initiatives.

We are seeking a Physical Design Manager.
Meet the Team:
Physical Design team within Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
As the Physical Design Manager, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

We are seeking a Physical Design Technical Leader.
Meet the Team
Physical Design team within is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs.
We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility.
Your Impact:
You'll be part of the Silicon One team, which is at the heart of our software and ASIC design efforts.
You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning.

Required ASIC Leader
Meet the Team
Join the Silicon One Front-End Design team, at the core of our silicon development. Our engineers cover the full spectrum of chip design: definition, architecture, micro-architecture, RTL design, verification, signoff, and validation.
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact
Review micro-architecture specifications
Supervise verification team members and provide professional guidance
Implement Verification environment UVM based
Collaborate with Design engineers to resolve bugs and achieve coverage closure
Work with the firmware/Lab teams to verify chip flows
Perform debug, root-cause analysis, and post-silicon validation in the lab.

Required ASIC Design Engineering Technical Leader
Meet the Team
We leverage cutting-edge silicon technologies and methodologies to develop the largest-scale and most advanced devices, pushing the boundaries of whats possible.
We are transforming the industry with a unified, programmable architecture powering our future routing portfolio and shaping the Internet for decades to come.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab.