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חברה חסויה
Location: Haifa
Job Type: Full Time
Required Verification Engineer
Job Description Summary
Responsible for running various verification activities on PET medical products that covers multi-disciplinary aspects from SW/HW, electronics, mechanics, physics, image quality and radiation - which is safety for users and monitored by a tag all the time.
Job Description:
Responsible for planning and implementing verification methodologies and ensuring proper fulfillment of system and sub-system requirements.
Responsible for reviewing various product designs, verifying its functionality in agile testing methods.
Responsible to determine the testing environments and tools.
Analyze and debug system failures and issue found during testing, while delivering detailed reports identifying these issues for further investigation.
Work closely with development teams
Non-hybrid, full-time position on site
Flexible on working hour, including 2-3 evening shifts (14:00-23:00) per week as needed
Working on global programs that required tight collaboration with global and Israel teams.
Requirements:
B.Sc. in Bio-Medical / Mechanical / Electronic Engineering / Or Equivalent Experience.
+3 years of experience in multi-disciplinary medical products manual/automation testing, with strong knowledge of software QA processes
Good documentation skills of test design and scripts for complete coverage of detailed system requirements
Quality focus, willingness to learn, versatility and adaptability.
Good organizational skills and strong written and verbal communication.
Excellent English communication skills, both written and verbal.
Advantages:
Experience >5 years as verification engineer in medical device (PET/SPECT) companies
Experience with Agile methodology
Experience with Linux and MATLAB
Experience with Python & automation development
Experience with test tools and frameworks (such as: ALM, Rally, Doors & Compass).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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8807249
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חברה חסויה
Location: Haifa
Job Type: Full Time
Required Lead Service Integrator (LSI)
Job Description Summary
The Lead Service Integrator is responsible for activities relating to enhancing services technology for Molecular Imaging systems integrating customer data, or capturing products reliability, availability, maintenance, safety, and other performance parameters.
Service activities for Molecular Imaging products (MI, PET and SPECT) include service-related system conceptual design, requirements development, FMEA, service features integration, and providing support to field engineers.
Duties include (but are not limited to):
The Service Engineer position is responsible for ensuring on-time delivery of service product features, technical publications, training, global parts availability, and service process validation. The position provides exposure to the entire system and requires communication with all functions in the organization and will be involved in the full life cycle of the product from definition to verification/validation and installed base support.
Development of service design concepts and features based on MI user needs and allocate to subsystems based on design concept decomposition and trade off studies.
Specifying CTQs and requirements, documenting service design, and participating in service-related verification activities.
Ensuring that MI systems, subsystems, or component designs meet service requirements, from install, troubleshooting, repair, to preventive and proactive maintenance.
Setting FRU strategies and interfacing with external organizations such as GPRS and Service Operations
Working with customers, field engineers and engineering to solve field issues.
Analyzing maintenance related aspects from the field and delivering and incorporating feedback results into new hardware, software, and service specifications.
Driving service metrics analyzing, reporting and improvements (I&W, spare part consumption, etc.)
Preparing all service documentation.
Requirements:
Required Qualifications:
BSc in Mechanical/ Electrical/ Biomedical Engineering, or Physics.
at least 3 years work experience in the Engineering/Technology & Service Engineering
Advantage - experience in more than one engineering position, either in a single or multiple workplaces
Experience in medical systems and independent by nature and Self-learner - advantages.
Desired Characteristics:
Strong oral and written communication skills. Demonstrated ability to analyze and resolve problems. Ability to document, plan, market, and execute programs.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8807203
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
4 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8782537
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior CPU Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, and system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning and test execution to collecting and closing coverage.
We're the driving force behind groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Knowledge of CPU/Processor architectures (e.g., pipeline, cache, memory subsystem, instruction sets, exceptions) like ARM, X86 or RISC-V, is highly beneficial for verifying processor cores or IP blocks.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8782626
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מודים לך שלקחת חלק בשיפור התוכן שלנו :)
חברה חסויה
Location: Haifa
Job Type: Full Time
Required System Engineer
Job Description Summary
The Systems Engineer has design responsibility to deliver customer workflow, feature functionality, product quality, reliability, serviceability, manufacturability, regulatory, compliance, and cost.
Activities include system conception, system analysis, requirements development, traceability and flow down, architecture/system design, FMEA, system integration, system optimization, developing/executing System Verification and Validation test procedures, and providing support to manufacturing and field issues.
Our Molecular Imaging in Israel is the largest diagnosis imaging development center in the world.
Our mission is to bridge the gaps between discovery, diagnosis and treatment with medical imaging innovations to help our customers deliver precise, personalized care through cutting-edge applications that change lives.
We do this through our powerful multidisciplinary team spans a broad variety of skills and capabilities - product managers, SW/HW/systems/mechanical engineers, physicists and clinical experts, sourcing, regulatory affairs, business leaders.
Responsibilities:
Duties include (but are not limited to):
Providing domain expertise to serve as the main integrator between all involved disciplines and functions to deliver the best quality product.
Working across functions and team boundaries to define, design, and implement the next generation of products, features and functionalities.
Working with customers, Marketing and field personnel to refine requirements which can be further developed by the engineering teams.
Developing methods to quantify subsystem interactions and their effects on image quality
Delivering and incorporating feedback results into new hardware, software and service specifications.
Decision making in cross-disciplinary and architectural aspects.
Apply expertise to help resolve urgent issues with current Molecular Imaging products.
Assist Program Manager in execution of projects within time and schedule.
Requirements:
B.Sc. in Biomedical/Mechanical/ Electrical/Software Engineering.
MSc in engineering - advantage.
Experience in medical systems - advantage.
At least 2 years of relevant systems engineering work experience in projects involving design and development of complex systems.
Advantage - experience in more than one system engineering position, either in a single or multiple work-places
General:
Independent by nature, Self-learner, Excellent communication skills
Proven ability to develop timely and effective solutions for challenging design problems.
Proficient in use of software tools for analysis and simulation (MATLAB, etc.)
Demonstrated ability to pursue tasks to completion.
Broad exposure to Mechanical/ Control/ HW/SW/Systems design, and technical depth in one or more engineering disciplines (Electrical, Mechanical, Software, Control, Physics, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8807236
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דיווח על תוכן לא הולם או מפלה
מה השם שלך?
תיאור
שליחה
סגור
v נשלח
תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior SoC Design Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work as part of a Research and Development team. You will build verification components, constrained-random testing, system testing, and drive verification closure. You will verify digital designs, collaborate closely with design and verification engineers on projects, and perform direct verification. You will build constrained-random verification environments that exercise designs through their corner-cases and expose all types of bugs. You will manage the full life-cycle of verification, which can range from verification planning, test execution, to collecting and closing coverage.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
Identify and write all types of coverage measures for corner-cases.
Debug tests with design engineers to deliver functionally correct design blocks.
Close coverage measures to identify verification holes and to show progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience with creating and using verification components and environments in standard verification methodology.
Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, or a related field.
3 years of experience with creating and using verification components and environments in standard verification methodology.
Experience with verification techniques, and the full verification life cycle.
Experience with performance verification of ASICs and ASIC components.
Experience with Application-Specific Integrated Circuit (ASIC) standard interfaces and memory system architecture.
Experience in four or more System on a chip (SOC) cycles.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8783523
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Design Verification Engineer, Networking, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Verification Engineer, you will be a part of the Research and Development team to verify digital designs, develop constrained-random test environments and drive system testing to closure. You will collaborate with design and verification teams, manage the verification life-cycle and uncover bugs through corner-case testing.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop and refine random verification environments using SystemVerilog/Universal Verification Methodology (UVM) or Specman to ensure effective test coverage.
Define and implement various coverage measures to capture stimulus and corner-case scenarios.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out.
Requirements:
Minimum qualifications:
Bachelor's degree in Electrical Engineering, or equivalent practical experience.
4 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).
Experience with Central Processing Unit (CPU ) implementation, assembly language, or compute System on a Chip (SOC).
Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
Experience creating and using verification components and environments in standard verification methodology.

Preferred qualifications:
Masters degree in Electrical Engineering or Computer Science.
2 years of experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or Application-specific integrated circuit (ASICs).
Experience with UVM, SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8785595
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
07/09/2026
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for a Design Verification Team Lead - a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Nitro system SoC, the foundation of AWS's virtualization, networking, and storage offload infrastructure.

It starts at product definition - we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written

It extends into software - we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack, with particular emphasis on networking workloads such as ENA and EFA

It reaches into physical design - we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality

It closes the loop - from spec to silicon, our verification touches every team and every stage of chip development

Key job responsibilities

- Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with a strong connection to networking flows (ENA/EFA).

- Verify IO sub-system features, including interconnect protocols and various accelerator engines.

- Develop and debug C embedded SW as part of hardware-software integration verification.

- Build and maintain UVM-based verification environments for various clusters and sub-systems.

- Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.

- Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).

- Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.

- Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.

- Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.
Requirements:
Basic Qualifications
- 8+ years of experience in design verification of complex SoC or ASIC projects.
- Strong communication skills with the ability to collaborate across design, software, and physical design teams.
- Proven track record leading verification of IO sub-systems, interconnect fabrics, or system-level integration blocks.
- Deep expertise in UVM/SystemVerilog-based verification environments.
- Experience driving verification from product definition through post-tapeout silicon validation.
- Experience with performance verification methodologies alongside functional correctness.

Preferred Qualifications
- Strong knowledge of ARM interconnect protocols (AMBA CHI/ACE/AXI) and coherency verification.
- Experience with IO virtualization verification (SMMU, TLB, page table walks, memory attributes).
- C/C++ embedded software programming and firmware-level debug skills
- Experience with hardware-software co-verification.
- Familiarity with networking data paths and offload architectures.
- Understanding of physical design aspects and their impact on functional verification (e.g., clock domain crossings, power-aware verification).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8813332
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Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
Required Senior Emulation Verification Engineer, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Responsibilities
Plan and execute the verification of digital design blocks by understanding specifications and working with design engineers to define key verification scenarios.
Develop, execute, and debug full-chip/system on a chip (SoC) tests on emulation platforms.
Collaborate with design engineers to debug tests and ensure functional correctness of design blocks.
Define and implement various coverage measures to capture stimulus and corner-case scenarios. Work with software and post-silicon validation teams to reproduce failures on emulation.
Drive coverage analysis to identify verification gaps and demonstrate progress towards tape-out. Explore new verification and emulation methodologies and implement them.
Requirements:
Minimum qualifications:
Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience.
8 years of experience with full-chip/SoC verification (e.g., test definition, creation, execution, and debug).
Experience developing full-chip/SoC tests using these environments/tools: ASM, C, C++, Perspec, Threadmill, OS, or drivers.
Experience with execution and RTL/firmware/software debug on hardware emulation (e.g., ZeBu Server, Palladium, Veloce) or FPGA (e.g., EP, HAPS, Protium).
Experience with design debug tools (e.g., Verdi, Verisium).
Experience with coding and scripting in C, C++, Perl, TCL, or Python.

Preferred qualifications:
Experience in embedded software and firmware (e.g., Linux drivers, firmware validation).
Experience with associated electronic design automation (EDA) tools, automation, and flow enhancements.
Experience with coding in Verilog/SystemVerilog for design.
Understanding of SoC architecture and interfaces (e.g., CPU, DDR, PCIe, interconnect, Ethernet, etc.).
Understanding of register transfer level (RTL) to emulation/field-programmable gate array (FPGA) flows including emulation test benches (e.g., transactors/accelerated verification intellectual properties (VIPs), hybrid, in-circuit emulation).
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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עדכון קורות החיים לפני שליחה
8785654
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Location: Haifa
Job Type: Full Time
Required Lead Clinical Applications Engineer
Job Description Summary
The Lead Clinical Applications Engineer is a role within R&D, focused primarily on new product introduction and continuous improvement of post-market Nuclear Medicine and/or PET-CT imaging systems and related software. The role provides clinical and application expertise to product and engineering teams, ensuring solutions meet clinical needs, deliver strong image quality and quantification, and perform reliably in real‑world use.
Working closely with R&D, system engineering, product management, service, and field teams and customers, this role translates clinical needs, customer feedback, and usage insights into practical system and software improvements, while supporting resolution of complex clinical and application‑related issues.
Job Description
Lead Clinical Applications Engineer
Key Responsibilities:
Serve as a clinical reference for Nuclear Medicine and PET-CT applications and workflows within R&D programs.
Support investigation of selected complex customer or field issues, translating findings into actionable inputs for product improvement.
Interface with product, software, algorithms, system engineering, hardware, UX, service, and field organizations as needed.
Translate clinical use cases and user needs into system and software requirements in collaboration with engineering teams.
Support design and validation of Nuclear Medicine and PET-CT applications, reconstruction methods, and workflow solutions.
Provide clinical input to decisions impacting image quality, quantification accuracy, dose, and user experience.
Participate in evaluation of AI‑enabled Nuclear Medicine and PET-CT, supporting clinical validation and performance claims.
Contribute to usability, clinical validation, and regulatory‑related documentation as required.
Requirements:
Required Qualifications
Bachelors degree in Biomedical Engineering, Medical Physics, or related field.
4+ years of experience in clinical applications, R&D, or system engineering in medical imaging (PET‑CT, Nuclear Medicine, or CT)
Solid understanding of medical imaging physics, reconstruction, quantification, and clinical workflows.
Experience working effectively in cross‑functional, collaborative environments, including product, engineering, field teams and end users.
Strong analytical skills and experience with quantitative image evaluation.
Proficiency with modern digital and AI‑based tools for analysis and productivity.
Strong communication skills in English and Hebrew.
Preferred Qualifications:
Masters degree in Biomedical Engineering, Medical Physics, or related field.
Hands‑on experience with commercial Nuclear Medicine and/or PET-CT systems.
Exposure to AI‑driven imaging or advanced reconstruction solutions.
Experience in global or matrixed R&D organizations.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
עדכון קורות החיים לפני שליחה
עדכון קורות החיים לפני שליחה
8806330
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