We are looking for a highly experienced Quantum Control Systems Engineer (Application Validation Team) who embodies ambition and positivity. Someone who can passionately take ownership of their responsibilities, collaborating effectively with remote teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
As a Quantum Control Systems Engineer on the Application Validation Team, you will be responsible for validating the software and hardware systems that drive quantum computing operations, ensuring that programs ranging from calibrations to error correction procedures perform as expected on all our quantum controller hardware. This includes designing, implementing, and testing scalable software and hardware frameworks across various qubit types, as well as developing tools that support the validation and execution of control software across different configurations and execution platforms.
Your role will also involve developing a robust software infrastructure that automates the validation process, integrates with real hardware systems, and supports continuous integration (CI) and continuous deployment (CD) pipelines.
This is an exciting opportunity to work at the forefront of quantum computing technology while ensuring the performance, reliability, and scalability of cutting-edge control systems.
Join us in this exciting journey to redefine the future of quantum computing.
Responsibilities:
Quantum Computing Routine Validation: Validate quantum computing programs on our quantum controllers, including calibration procedures, error correction routines, and other algorithms, ensuring they meet the required performance standards.
Scalable Routine Design: Design and implement scalable quantum routines in Qua and other quantum computing languages, optimizing various qubit types and quantum computing architectures.
Framework Development: Develop tools and frameworks that support validation, ensuring scalability and integration into our hardware and software development process.
Automated Testing and CI/CD Integration: Build and maintain automated testing systems, incorporating CI/CD processes to ensure seamless integration and validation of quantum control software on real hardware.
Data Analysis: Analyze measurement data from quantum controllers, using this data to improve implementations across the whole software stack.
Cross-Functional Collaboration: Work closely with quantum physicists, customers software engineers, and hardware engineers to troubleshoot issues, refine quantum routines, and ensure the overall system's performance.

Required Senior Verification Engineer, Digital Signal Processing, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you own the verification strategy for high-speed Physical Layer (PHY). You aren't just looking for RTL bugs, you are looking for system-level failures. You will lead the effort to verify how the digital DSP interacts with the analog front-end.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the verification strategy for high-speed PHYs (112G/224G), defining the test plan for top-level integration and mixed-signal boundaries.
Architect and implement mixed-signal verification flows using Real Number Modeling (RNM) or SystemVerilog-AMS to verify the interaction between Analog Front Ends (AFE) and digital DSP.
Design specialized testbenches to verify the stability, convergence time, and tracking capabilities of adaptive algorithms (e.g., LMS, Zero-Forcing) across Process, Voltage, Temperature (PVT) corners.
Develop tests that simulate real-world data center conditions, including link bring-up, auto-negotiation, and error-recovery protocols.
Act as the primary verification interface for the Signal integrity and Power Integrity (SI/PI) and Analog teams, ensuring that physical channel impairments (loss, crosstalk, reflections) are accurately reflected in the Design Verification (DV) environment.

We are seeking for a passionate and skilled Validation Engineer to join our core R&D team. As a Validation Engineer, you'll play a critical role in ensuring the quality, reliability, and performance of our state-of-the-art quantum control systems. You will design, develop, and execute validation plans for complex hardware-software systems, contributing directly to the advancement of quantum technologies.
This role is ideal for engineers with good programming skills, a strong technical culture, and a passion for working at the intersection of software, hardware, and quantum science.
Main Responsibilities:
Design and Implement Validation Methods: Design, implement and execute comprehensive validation test plans for our quantum control platforms and solutions
Automated Tests and Automation Frameworks: Contribute to the development of automated testing infrastructures to streamline validation processes and implement system tests based on the defined test plans
AI/ LLM Tools: Apply AI/LLM tools to accelerate test code generation and continuously improve the validation toolchain, driving measurable gains in engineering productivity
Data Analysis: Collect, interpret, and document data from system tests/experiments to assess system performance and identify areas for improvement
System Debugging & Troubleshooting: Identify, reproduce, and analyze issues across system components with other engineering teams
Collaborate Across Teams: Collaborate closely with R&D and product teams to define test coverage and quality acceptance criteria
Release & Quality Assurance Process: Participate in regression testing and CI/CD for new feature rollouts and product releases
Maintain and Improve Test Setups: Oversee the setup, calibration, and enhancement of test equipment and environments

We are looking for some exceptional talent to join our Innovation team as an Applied Physics & EO Researcher.
Your Day to Day:
Ownership of complex experimental systems and meeting challenging targets under tight deadlines
Lead and contribute to multidisciplinary research projects across advanced technologies and emerging domains
Design, execute, and analyze experiments, simulations, and proof-of-concept studies
Translate theoretical physics concepts into scalable, real-world applications
Collaborate closely with engineering, product, and cross-functional teams to drive innovation
Stay at the forefront of scientific and technological advancements and identify opportunities for integration
Present research findings clearly to both technical and non-technical stakeholders

We are global, with HQ in NYC and R&D centers in Tel Aviv, New York, Finland, Berlin, Belgium and San Diego. We work in a fast-paced environment and have a lot of challenges to solve. If you like to work in a huge scale environment and want to help us build products that have a huge impact on the industry, and the web - then your place is with us.
What you will do:
Develop and improve models that analyze millions of videos and images every day across the web, Smart TVs, YouTube, Facebook, Twitter, Instagram, TikTok and more to detect the content categories they are about.
Work alongside experienced data scientists and engineers in a cutting-edge environment, contributing to advanced ensembles of models at huge scale.
Participate in the full development cycle - from research and experimentation through to deployment - gaining hands-on experience with production ML systems.
Leverage AI-powered tools and assistants as part of your daily workflow to accelerate research, coding, and analysis.
Help advertisers avoid negative or irrelevant content and target what's most relevant to their brand, keeping the web free for everyone.

We are seeking an experienced Embedded Software Engineer to join a team of top-tier professionals developing a high-performance system built on the AMD/Xilinx Zynq UltraScale+ RFSoC platform. This system will form the core technology behind the companys future RF and wireless products, spanning secure cellular communications, signal-emission detection, and protection against communications exploitation.
Responsibilities include:
Develop embedded C/C++ software for the RFSoCs Arm Cortex-A53 and Cortex-R5F processors in embedded Linux, FreeRTOS, and bare-metal environments.
Configure RF ADC/RF-DAC resources, AXI and DMA data paths, interrupts, clocks, NCOs, interpolation, decimation, and multi-tile synchronization.
Support RFSoC board bring-up, FPGA integration, debugging, and system validation.
Implement detection infrastructure and embedded algorithms to identify anomalous or unauthorized activity.
Develop and optimize end-to-end, high-performance PCIe/DMA software solutions across embedded and host platforms, including low-level Linux drivers, user-space components, APIs, libraries, multithreaded applications, and automated performance testing.

Our networking is a world-leader in building the most powerful supercomputers in the world which drive the AI and HPC industry. These rely on high performant network ASICs which connect GPUs at scale for efficient data transfer and compute. We are looking for a hardware performance modeling architect to join our team and build a network simulator used for the design, optimization and exploration of our future networking chips. The role is cross-disciplinary, collaborating with hardware and software teams across the wider company. You will solve complex problems, develop innovative solutions and be instrumental in determining the architecture of our next generation networking solutions.

What you'll be doing:

Define the Network Adapter chip architecture end to end from the market requirements through design and all product life cycles (post/pre-silicon, on deployments). Work with related industry standards & customers on deploying your tech.

Collaborate with teams across teams (physical design, logic design, system software, firmware, applications)

Develop cycle-accurate simulation components to evaluate and analyze micro-architecture and architectural options.

Explore innovative ideas to improve and optimize our chip systems performance.

Serve as a focal point within the organization and distribute the knowledge that you acquire.

We are seeking a motivated Senior System Validation Engineer to join our growing post-silicon validation team in Israel and support next-generation connectivity products for AI and data-center applications.
In this role, you will perform system-level post-silicon validation, characterization, and debug across silicon, hardware, firmware, and software. You will support silicon bring-up and PVT/corner testing, develop and execute functional and system validation tests, analyze results, and work with cross-functional teams to identify and resolve complex system issues.
This is a highly hands-on lab position. The primary location is Haifa, with temporary support at the Ramat Gan lab as needed.
Key Responsibilities:
Develop and execute post-silicon functional and system validation from silicon bring-up through production readiness.
Run PVT, silicon corner, stress, characterization, and qualification testing across a wide range of operating conditions.
Develop validation tests to verify functionality, performance, stability, power, and operating margins.
Debug issues across silicon, hardware, firmware, drivers, and system software.
Validate high-speed interfaces such as PCIe, CXL, Ethernet/SerDes, and DDR, as well as common system interfaces.
Develop Python scripts and automation to improve validation coverage, regression, and test efficiency.
Analyze validation data, identify issues and trends, and drive problems to root cause and closure.
Work closely with hardware, architecture, firmware, software, design, and DV teams to investigate and resolve issues.
Support the transition of new silicon from initial bring-up to a qualified, production-ready product.
Operate system platforms and laboratory equipment to support validation and debug.
Document test results, issues, root cause, and recommendations and communicate findings clearly.

Required ASIC Design Verification Engineer, Digital Signal Processing
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
In this role, you will define and execute the verification strategy for high-speed Physical Layer (PHY) digital blocks. This role focuses on the functional and mathematical verification of complex DSP algorithms, digital-analog boundaries, and signal processing logic. This position requires a strong technical foundation in communication theory, fixed-point arithmetic, and mixed-signal co-simulation.
Responsibilities
Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using Real Number Modeling (RNM) or SystemVerilog-AMS.
Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for digital signal processing blocks.

Required Power and Signal Integrity Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives.
You'll set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.
The ML, Systems, & Cloud AI (MSCA) organization designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all services (Search, YouTube, etc.) and Cloud.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities:
Design and optimize power distribution networks (PDN) across chip, package, and board levels. This includes managing power/ground planes, decoupling capacitors, and power gating strategies.
Conduct both pre-layout and post-layout power integrity simulations to analyze power and ground noise (SSN/SSO), voltage drops (IR drop), and electromagnetic interference (EMI).
Implement and verify low-power design methodologies, such as multi-voltage designs and clock gating, using power intent formats like UPF/CPF.
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR), Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.