דרושים » חשמל ואלקטרוניקה » Senior Staff DSP Design Engineer, Cloud

Required Staff Architect, Digital Signal Processing, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Engineer on the Digital Signal Processing team, you will be a technical leader responsible for architecting and developing the core algorithms that power our next-generation data center interconnects. You will leverage your expertise in communication theory, forward error correction (FEC), and modulation to design novel, low-complexity solutions that push the boundaries of speed and reliability.
In this role, you will not only define the technical direction for critical projects but also mentor other engineers and collaborate across hardware and software teams to bring your goal to life in silicon.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Lead the architecture, design, and implementation of digital signal processing (DSP) algorithms for high-speed optical communication systems. Drive the long-term technical roadmap for our signal processing and communication architectures by staying current with academic and industry trends.
Develop and analyze novel forward error correction (FEC) and modulation schemes to optimize for performance, power, and complexity tradeoffs.
Create comprehensive system-level models using tools like Matlab, Python, or C++ to simulate and validate algorithm performance.
Collaborate closely with logic design, verification, and software teams to ensure the successful implementation, integration, and bring-up of algorithms in custom silicon.
Provide technical leadership and mentorship to a team of DSP and communication systems engineers, fostering innovation and engineering excellence.

Required Senior Digital Signal Processing Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be responsible for turning communication theory into efficient, bit-exact silicon logic. You will take high-level models and transform them into the high-speed DSP blocks that anchor our next-gen architecture.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Design and implement DSP algorithms for high-speed PHYs, focusing on feed-forward equalization (FFE)/decision feedback equalization (DFE) and timing recovery loops.
Perform fixed-point analysis to minimize bit-width (area/power) while maintaining the required signal-to-noise ratio (SNR).
Develop bit-exact C++/SystemC models to verify register-transfer level (RTL) against architectural intent.

Required Senior Analog Design Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Analog Design Engineer, you will design and integrate analog sub-systems. You will be responsible for ensuring the Analog Front-End (AFE) communicates flawlessly with the Digital Signal Processor (DSP), the package and silicon are a single electrical entity. Your work will bridge the analog and digital worlds to enable industry-leading performance.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Own the architecture and implementation of a major sub-component, such as the entire receiver AFE or the clocking/Phase-Locked Loop (PLL) distribution network.
Design the critical "suspension system" (e.g., Equalization/CTLE, ADC) that allows the digital core to function perfectly despite a noisy, high-loss channel.
Lead the definition and design of test chips to verify out novel topologies and circuit techniques in next-generation Gate-All-Around (GAA) nodes.
Collaborate with DSP, firmware, and system architects to define hardware/software partitioning and interface specifications.
Provide technical guidance and mentorship to engineers on the team.

Required Senior DFT Lead
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.
In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next-generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.
Responsibilities
Drive and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Collaborate with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Oversee DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Required Senior Post-Silicon Validation Engineer, Networking
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
We are building a new team to lead the post-silicon validation efforts for our cutting-edge product. We're looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact.
As a Silicon Validation Engineer, you'll play a pivotal role in the validation of our custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Conduct in-depth analysis into the architecture and microarchitecture of complex hardware units and features, such as packet processing pipelines and advanced networking capabilities.
Develop comprehensive post-silicon validation test plans based on a thorough understanding of the design and specifications.
Write, execute, and debug validation tests using Python or C/C++, running on Pre-Silicon (Pre-Si) emulation platforms and primarily on the silicon.
Lead the bring-up, troubleshooting, and debug efforts on silicon, identifying root causes of hardware and software issues.
Contribute to the development of test infrastructure and methodologies to improve validation efficiency and coverage.

Required Senior Silicon Physical Design Engineer
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.

Required SoC DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Required Senior Silicon DFT Engineer, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout.
Responsibilities
Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs.
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage the DFT team's workload and deliverables, provide technical leadership and guidance to the team.
Lead DFT execution of a silicon project (e.g., planning, execution, tracking, quality, and signoff).

Required RTL Design Technical Lead, Servers, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use the ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
Responsibilities
Lead the Design Activities at IPs, SubSystems(S.S) and SoC.
Plan, execute, track progress, assure quality, report status of the assigned activity.
Lead a team of designers both directly and in teams.
Define the Block/SoC level design documents such as Micro Architectural Specifications.
Own IP, S, SoC strategies for clocks, resets, and debugs. Enforce global methodologies and drive enhancements.

Required Design Verification IP Lead, Cloud
Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will work to shape the future of an edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive the distributed inference technology that powers real-time systems where latency and reliability are mission-critical.
You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy complex AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens.
Our mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
Lead the verification of an edge AI IP, to be used in our edge-AI products.
Lead a team of chip verification engineers. Plan tasks, allocate people, hold verification design/code reviews, and drive verification execution.
Plan the verification of digital design blocks, including writing test plans, and other verification documents.
Code development of verification features and capabilities, and participate in RTL debug.
Work closely with Architecture, Software, Design, and Physical Design stakeholders to make technical decisions and represent project status throughout the development process.