דרושים » חשמל ואלקטרוניקה » Logic Design Engineer

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לפני 13 שעות
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
We are looking for an excellent design engineer to join our team and build our state-of-the-art control and orchestration platform. We are looking for a highly talented and motivated person, who is a real team player and which can collaborate closely with engineers from other disciplines and quantum physicists
Responsibilities:
Designing a configurable and very low-latency challenging RTL
Bringing the state-of-the-art FPGA to its limits with regards to logic & timing optimization
End2end ownership of the entire coding process (Arch->uArch->Design->Implementation)
Learning system and SW requirements for proper implementation of HW-SW interface.
Requirements:
BSc in electrical/computer engineering or relevant military background
At least 4 years of experience
Proven track record in RTL coding with System Verilog
Experience with System Verilog
VCS, Vivado - Advantage.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an experienced Design Engineer to join the YU design team and develop the next generation technologies.

As a design engineer in the YU design team, you will participate in definition and implementation of our boot and chiplet control technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated boot components into various projects and using state-of-the-art technologies.
As a member of our YU design team, you will participate in defining various boot and chip controller features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:
B.SC./ M.SC. in Computer Engineering/Electrical. Engineering/Communication Engineering.
5+ years of practical experience.
Exposure to rtl implementation and coding.
Familiarity with verification tools.
Strong debugging, problem solving and analytical skills.
Strong communication and social skills are required.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
High Level of English.

Ways to stand out from the crowd:
Prior Design or Verification experience.
Experience in developing sophisticated design blocks.
Knowledge in Mixed Signals, Analog, and Behavioral Models for Verification.
Knowledge in Chip boot and Infrastructures.
Experience in working with back-end on area, power and timing closures.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for an experienced DFT Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.

As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.

Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
What we need to see:

B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.

5+ years of practical experience.

Exposure to rtl implementation and coding.

Familiarity with verification tools.

Strong debugging, problem solving and analytical skills.

Strong communication and social skills are required.

Ability to work in a geographically diverse team environment.

Self motivated, independent and target oriented.


Ways to stand out from the crowd:

Prior Design or Verification experience.

Experience in developing sophisticated design blocks.

Integration of design elements to large cluster or full-chip.

Experience in working with back-end on area, power and timing closures.

Scripting ability.
This position is open to all candidates.
 
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10/06/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
We're looking for an exceptional senior Chip Design Engineer to join our Nitro team and help shape what comes next. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match- powering hundreds of thousands of businesses across 190 countries.

As a Senior Chip Design Engineer on the Nitro team, you will take full end-to-end ownership of one or more critical IP blocks within the product, guiding them from micro-architecture definition through RTL design, debug, synthesis, timing closure, and final sign-off before tape-out. Your work will ship in silicon that powers AWS at global scale.
You'll partner closely with the Verification and Emulation teams to shape test plans, review coverage, and close gaps early in the design cycle. Beyond your own IP, you'll collaborate across disciplines with Product Definition, Software, Physical Design, and Verification teams to deliver a fully integrated, production-ready chip.

Key job responsibilities
Full ownership of one or more IPs within the product:
Micro-architecture definition.
RTL coding and debug.
Synthesis and timing closure.
Sign-off before tape-out.
Supporting the Verification and Emulation teams: Test plan development, coverage review.
Ensuring the chip meets quality and reliability standards.
Collaborating with cross-functional teams, including Product Definition, Verification, Software, and Physical Design.
Requirements:
Basic Qualifications
- 6+ years of experience in chip design.
- Hands-on experience in micro-architecture and RTL design (Verilog / System Verilog).
- Scripting expertise in C*, Perl, Python, or TCL.
- BSc in Computer/Electrical Engineering.
- Strong communication and collaboration skills.
- Strong leadership skills and ability to own complex units.

Preferred Qualifications
- Bachelor's degree in computer science or equivalent.
This position is open to all candidates.
 
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4 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Engineering team works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.



Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!



What youll be doing:

You will be in charge of state of the art Design for Test/ATPG flows and implementation.

Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.

Inventing and maintaining automation flows that provide the short test time to production.
Requirements:
What we need to see:

5+ years of hands on DFT/ATPG experience knowledge & technical experience in DFT ASIC Design and in ATPG tools.

Strong programming skills in scripting languages.

BSc. in Electrical Engineering or Computer engineering.

Quick learner, proactive and self-motivated, eager to learn and contribute, sense or ownership, commitment, and responsibility.



Ways to stand out from the crowd:

Knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.

Experience in Mentor TestKompress ATPG tool and retargeting flow.

Programming languages: TCL, PRL, Phyton & Unix shell scripts.

Experience with ATE and Silicon bring-up.
This position is open to all candidates.
 
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לפני 13 שעות
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time and Hybrid work
Required Micro-Architect
Description
A global leader in control systems for quantum computing, a field on the verge of exponential growth.
Our innovative hardware and software mark a groundbreaking approach in quantum computer control, scaling from individual qubits to expansive arrays of thousands.
At the core of the company lies a passionate and ambitious team committed to reshaping the construction and operation of quantum computers.
Our work is fueled by a deep understanding of customer needs, driving us to deliver unparalleled solutions in this revolutionary field.
Join our cutting-edge hardware development team as Micro-Architect and play a key role in defining and implementing the micro-architecture of advanced digital logic components.
What You'll Do:
Define and develop micro-architecture for complex logic blocks - from concept through high-quality RTL implementation
Collaborate closely with architecture, verification, design and software design teams
Write clear and detailed design specifications and drive architectural trade-off analysis
Optimize for performance and area
Contribute to innovation, methodology improvements, and technical leadership within the team.
Requirements:
B.Sc. or higher in Electrical Engineering, Computer Engineering, or related field- Must
8+ years of experience in RTL design using Verilog/SystemVerilog- Must
Proven experience in designing micro-architecture for complex systems
Strong system-level understanding and problem-solving skills.
This position is open to all candidates.
 
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26/05/2026
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking to hire a talented Verification Engineer to join our VLSI group in Tel Aviv.
You will work alongside other talented engineers to develop our cutting-edge AI chips. If you are motivated and skilled in VLSI and excited about AI, we want to meet you!
Responsibilities:
Collaborate with architecture and design teams to define and implement comprehensive testcases for NN processor and SoC blocks and flows.
Maintain, enhance, and scale the UVM‑based verification environment to support efficient and robust verification.
Own end‑to‑end verification of system flows to ensure the design is fully functional, correct, and meets performance expectations.
Drive root‑cause analysis and debug across RTL, testbench, and system layers to ensure high‑quality design closure.
Define, track, and close functional and performance coverage to guarantee verification completeness.
Continuously improve verification methodologies, automation, and workflows to increase productivity and coverage efficiency.
Requirements:
B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or a related field from a leading university.
3+ years of hands‑on experience in ASIC design or verification.
Strong knowledge of SystemVerilog and the UVM verification methodology.
Experience with SoC‑level verification is an advantage.
Excellent problem‑solving abilities and strong communication skills.
Proficient in written and spoken English and comfortable collaborating with a global team.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Tel Aviv-Yafo
Job Type: Full Time
We are now looking for a Senior Chip Design Engineer for the Switch Silicon group.

As a Chip Design Engineer at NVIDIA's Networking business unit, you'll join a group of passionate engineers to design and implement the next generation pioneering Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!

What you'll be doing:

Work in a combined design and verification team which develops some of the switch silicon core units.

Build reference models, verify and simulate chip blocks/entities according to specifications.

Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, and FW.
Requirements:
What we need to see:

Proven experience in RTL design or RTL verification.

4+ years of relevant experience.

Previous experience in networking - an advantage.

B.Sc. in Electrical Engineering or Computer Engineering, or equivalent experience.

A great teammate with good communication and social skills.
This position is open to all candidates.
 
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1 ימים
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing full-chip physical design methodologies, Physical Verification development and support through all the projects, Tapeout activities for implementation of networking chips and SOCs.

Work closely with Full Chip Layout owners and block owners, project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art FCL physical design problems that are needed for our chips.

We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.

Participating and developing flow and tool methodologies for fullchip, physical design verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

You should have at least 5+ years of hands-on Full-chip layout and Physical Verification experience, demonstrating your proven expertise.

A strong background in Physical Verification methodology, including DRC / LVS / ANT / ERC / DFM in advanced process nodes is necessary.

Proficiency using Python, Tcl, Shell, Make scripting.

Experience in Linux environments.

AI tools orientation or alternatively a desire to learn.

Familiarity with physical build EDA tools, including Synopsys (ICC2/FC) and Cadence (Innovus).

Familiarity with Physical Verification tools: Synopsys (ICV), Siemens (Calibre)

Self-motivation, attention to detail, and good interpersonal skills.


Ways to stand out from the crowd:

Experience with data collection and analysis

Experience in methodology definition / flow owner of Full-chip / Place and Route

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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20/05/2026
חברה חסויה
Location: Tel Aviv-Yafo and Haifa
Job Type: Full Time
We're looking for a talented SoC Integration Lead to join our Nitro team and help shape what comes next. You will spearhead the SoC integration activities of sophisticated networking chips, collaborating closely with Architecture, RTL Design, Physical Design, Package Design, Verification, Software, DFT, and additional teams in a dynamic, open, and fast-paced environment. As a member of the Nitro project, you will have influence over the device through its entire lifecycle from product definition to mass production. You'll work alongside a world-class, fast-moving engineering team, take full ownership of critical IP blocks, and see your work deployed at a scale no other platform can match, powering hundreds of thousands of businesses across 190 countries.

Key job responsibilities
Take full ownership of SoC integration, including IPs development, partitioning, clock domain crossing (CDC), reset domain crossing (RDC), exploratory synthesis, and design quality verification.
Drive chip-level design implementation by partnering with multiple teams including Architecture, RTL Design, DFT, Verification, System Verification, STA, and Physical Design.
Oversee the creation of SoC-level IP blocks such as fabrics, interfaces, and security modules.
Lead RTL integration activities including micro-architecture definition, RTL coding and debug, synthesis and timing closure, and sign-off.
Address diverse functional and structural challenges, encompassing functional debugging, physical design preparation, emulation, and design quality issue resolution.
Contribute to the creation and implementation of design flows and automated solutions that facilitate efficient SoC development.
Support Verification and Emulation teams through test plan development and coverage review.
Ensure the chip meets quality and reliability standards while delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.
Requirements:
Basic Qualifications
- BSc in Computer/Electrical Engineering.
- 10+ years of hands-on experience in chip design.
- Strong practical expertise in micro-architecture and RTL design (Verilog / SystemVerilog).
- Competency in scripting languages (Python, Perl, Bash, or Tcl).
- Strong communication, collaboration, and leadership skills.
- Demonstrated ability to own and drive complex integration units end-to-end.

Preferred Qualifications
- Strong knowledge of protocols (AXI, CHI, DDR, Networking, PCIe).
- Experience with Network-on-Chip (NOC) architecture.
- Knowledge of coherent and non-coherent fabric design.
- Comprehensive SoC development cycle expertise (Synthesis, STA, CDC, Lint).
- Knowledge of Design Automation tools and techniques.
- Demonstrated commitment to quality standards and experience delivering to physical design teams, emulation platforms, firmware developers, and other stakeholders.
- Advanced degree in a related technical field.
This position is open to all candidates.
 
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26/05/2026
Location: Tel Aviv-Yafo
Job Type: Full Time
we are looking for a Image Processing Algorithms Engineer.
You will be responsible for defining end-to-end solutions for image signal processing algorithms, both classical and deep learning-based, from the algorithm level to the system level. You will bring your own hands-on expertise, as well as technical leadership, to see these solutions come to life from inception to full implementation.
You will design ISP components and take them from proof-of-concept to production, pushing image quality to a cutting-edge level. You will survey both academic literature and product-grade solutions, then design and implement dedicated solutions optimized for embedded HW. In addition to striving for best possible image quality, you will be responsible for leading the end-to-end implementation via collaboration with SW and HW implementation teams, targeting deployment to Vision Processor.
Responsibilities:
Serve as a domain expert in the field of image enhancement for video cameras. In particular, you will serve as the technical focal point for your projects, owning and leading the end-to-end technical aspects, while collaborating with external partners, internal teams, other algorithms engineers and cross-functional experts.
Translate high-level product requirements to system ISP building blocks and drive R&D efforts to implement them.
Implement proof-of-concepts, based on both your own ideas as well as taking ideas from publications, and carrying these from theory into practice that fits product requirements.
Evaluate and test your solutions considering both image quality and overall system behavior, benchmarking against existing solutions and baselines. Iterate and improve in order to reach superior results or a better quality/performance tradeoff.
Requirements:
MSc in EE/CS or similar.
6+ years of experience in R&D of image processing algorithms with proven track record of technical excellence and leadership.
4+ years of experience in R&D of deep learning-based algorithms, with demonstrated and quantified improvements of the deep learning component(s) compared to baselines.
Experience developing image processing algorithms deployed to embedded HW and real time systems, including their restrictions and considerations.
Experience leading algorithmic efforts via R&D collaboration of a few algorithms engineers, in addition to leading end-to-end implementation across teams.
Proficiency in Python, strong programming skills and ability to design and implement algorithmic solutions.
Strong analytic skills and ability to quickly learn new disciplines, new frameworks and tools.
Strong interpersonal communication skills, can-do attitude, self-driven to make things happen from theory to practice.
Advantages
PhD in EE/CS with a thesis in image processing.
Experience developing deep learning-based algorithms which are deployed to embedded HW, including their architecture and optimization process.
Experience with video processing, including temporal features like temporal denoising, stabilization, etc.
Academic publications accepted to top-tier conferences in relevant domains.
System level experience and understanding of complex multi-disciplinary systems.
This position is open to all candidates.
 
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