דרושים » הנדסה » SW Engineering Manager - Performance Modeling

Required Software Engineer, CPU Performance Modeling, Cloud
About the job
Our software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to our needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward.
In this role, you will work with System teams and the CPU Architecture team to develop an understanding of the Central Processing Unit (CPU), System on a Chip (SoC), performance metrics, benchmarks/measuring tools, and available optimization knobs. You will define methods and technologies to model CPU performance at different accuracy levels by supporting architectural explorations and decision making. You will correlate performance projections with measured post-silicon data.
Responsibilities
Write product or system development code.
Design, develop, test, deploy, maintain, and improve Central Processing Unit (CPU) software modeling and other software tools.
Manage project priorities, deadlines, and deliverables.
Collaborate with hardware and software CPU Architecture teams, SoC performance modeling team, and other Software teams.

We are looking for a highly experienced Real-Time C++ Team Leader who embodies ambition and positivity.
Someone who can passionately take ownership of their responsibilities, leading a talented team while collaborating effectively with remote and on-site teams to not only meet but exceed our objectives and fulfill the evolving needs of our expanding customer base.
The Real-Time C++ component is at the core of our Quantum Orchestration Platform - it serves as the driver for the Pulse Processing Unit (PPU), our proprietary VLSI-based engine. This component is responsible for preparing, loading, and launching the execution of quantum-computing workloads, operating at extreme performance levels to maximize hardware utilization and minimize software overhead.
Responsibilities
Lead and grow a team of real-time C++ engineers, fostering technical excellence, collaboration, and professional development.
Own the architecture and development of the real-time C++ layer that drives the Pulse Processing Unit (PPU), our company's proprietary VLSI-based processor.
Design and implement high-performance software for preparing, loading, and launching quantum-computing workloads with minimal latency and maximal hardware utilization.
Drive relentless optimization of the software stack to minimize SW overhead in the critical path, ensuring the hardware operates at peak throughput.
Collaborate closely with VLSI, compiler, and architecture teams to ensure seamless software-hardware integration across the quantum control stack.
Define and uphold engineering standards, code quality practices, and performance benchmarking methodologies for the team.
Contribute hands-on to the codebase - designing, reviewing, debugging, and profiling performance-critical code paths.
Participate in cross-team technical planning, roadmap definition, and alignment with product and customer needs.

Required Design Team Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Design Team Manager within the Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
In this role, you will oversee the Intellectual Property (IP) and SoC VLSI design cycle from architecture to production. You will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads. You will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and System-on-Chips (SoCs).
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Required Design and Power Methodology Manager, Servers, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design and Power Methodology Team Manager within the Server Chip Design team, you will be responsible for managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

we are seeking an experienced Engineering Team Lead to head one of our three engineering teams. This team will comprise BE, FE and mobile developers, and a QA engineer. As the team lead, you will be responsible for guiding the team, ensuring successful delivery of projects, and fostering a culture of collaboration and continuous improvement.
As a Team Lead , youll tackle complex business logic, drive improvements in engineering processes, and guide your team through architectural and technical challenges. Youll build alignment, trust, and motivation across your team and R&D, shaping how we deliver software, collaborate as an organization, and provide an exceptional experience for travelers. This role is for someone seeking real impact, ownership, and the chance to lead talented engineers through meaningful technical and product challenges.
Responsibilities:
Lead, mentor, and manage a multidisciplinary team of backend, frontend, mobile developers, and QA engineers.
Oversee the design, development, testing, and deployment of high-quality software solutions that align with business goals.
Collaborate with product managers, designers, and other stakeholders to define technical requirements, set priorities, and establish project timelines.
Ensure adherence to best practices in software development, including code reviews, testing, and continuous integration and delivery (CI/CD).
Facilitate effective communication and collaboration within the team and across other departments.
Identify and address technical challenges, providing guidance and support to team members.
Monitor and improve team performance, productivity, and overall efficiency.
Stay updated with industry trends and emerging technologies, advocating for their adoption when appropriate.
Foster a positive and inclusive team culture that encourages innovation, learning, and personal growth.

Required Staff Architect, Digital Signal Processing, Cloud
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Staff Engineer on the Digital Signal Processing team, you will be a technical leader responsible for architecting and developing the core algorithms that power our next-generation data center interconnects. You will leverage your expertise in communication theory, forward error correction (FEC), and modulation to design novel, low-complexity solutions that push the boundaries of speed and reliability.
This is an executive role where you will not only define the technical direction for critical projects but also mentor other engineers and collaborate across hardware and software teams to bring your goal to life in silicon.
Responsibilities
Lead the architecture, design, and implementation of digital signal processing (DSP) algorithms for high-speed optical communication systems. Drive the long-term technical roadmap for our signal processing and communication architectures by staying current with academic and industry trends.
Develop and analyze novel forward error correction (FEC) and modulation schemes to optimize for performance, power, and complexity tradeoffs.
Create comprehensive system-level models using tools like Matlab, Python, or C++ to simulate and validate algorithm performance.
Collaborate closely with logic design, verification, and software teams to ensure the successful implementation, integration, and bring-up of algorithms in custom silicon.
Provide technical leadership and mentorship to a team of DSP and communication systems engineers, fostering innovation and engineering excellence.

We invite you to #UnleashyourCuriosity and join our ever-growing R&D organization.
What Youll Do:
Our engineering squads are responsible for critical domains and products that power our platform and support our users' ongoing relationship with us. The teams develop scalable web platforms, backend services, and applications, and are comprised of skilled engineers across the stack (backend, frontend, and data).
As a Squad Lead, you will be responsible for the team's technical leadership, domain design, and day-to-day execution. You will collaborate closely with product managers and business stakeholders to define priorities and deliver impactful solutions that align with key business goals. We are looking for someone who can drive end-to-end ownership, balance business needs with strong engineering practices, and help shape the direction of our products.
Responsibilities:
Among your key responsibilities, you will lead a highly skilled team that architects and builds scalable systems that serve our customers and partners.
Technical Architecture - Lead the technical architecture and system design for core products and services within your domain.
Team Leadership - Guide a multidisciplinary squad of frontend, backend, and data engineers through implementation, delivery, and iteration.
Stakeholder Collaboration - Work closely with product managers and business stakeholders to translate requirements into scalable technical solutions.
Strategic Alignment - Ensure development aligns with business objectives, long-term system health, and Sunbits engineering standards.
Quality - Conduct and lead design reviews, code reviews, and performance optimization efforts.
Culture Building - Drive a culture of technical excellence, ownership, and continuous improvement.
Operational Excellence - Oversee system reliability, monitoring, and incident response within your domain.

We are looking for a Senior DSP Software Engineer who will lead design and implementation of our innovative signal processing algorithms on the industry cutting-edge target platform, consisting of embedded cores, DSPs, and dedicated accelerators.
What will you do:
Perform analysis, design, implementation and validation of innovative MIMO imaging radar algorithms for next generation ADAS and autonomous
vehicles on our target platform
Participate in SW architecture design and perform signal processing algorithm porting & optimization
Address real-time constraints in a challenging memory/compute bound framework
Be part of a goal-oriented workgroup and dynamic research & development environment
Work in close collaboration with CTO and SW architecture team

Were seeking an outstanding hands-on System Software Engineering Manager with deep knowledge of low-level software design to lead a team of experts, and play a vital role in designing and implementing our firmware, drivers, and runtime components .
If you're passionate about hardware/software interaction and thrive in a collaborative, problem-solving environment - we want you!
Responsibilities:
Lead and mentor a team of 3-5 software engineers
Drive design and implementation of critical components such as our lo-level drivers and system-level software
Collaborate with cross-functional teams, including hardware engineers, to ensure seamless integration of software and hardware components.
Debug and troubleshoot issues at various levels of the software stack, from the host system to the emulator or RTL simulator.
Collaborate with the product management team to understand customer requirements and translate them into software solutions.

Required Senior Silicon Physical Design Engineer
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.
The AI and Infrastructure team is redefining whats possible. We empower our customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Cloud customers, and billions of users worldwide.
We're the driving force behind our groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Cloud, Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements.
Collaborate with cross-functional teams to debug failures or performance shortfalls and meet program goals in lab or simulation.
Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route, and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.