Hardware Engineer

לפני 19 שעות

Hardware Engineer

חברה חסויה

Location: More than one

Job Type: Full Time and Hybrid work

Essence Group, an Israeli high-tech company, is a global technology leader with a mission to develop and deploy innovative, cloud-based, end-to-end security and healthcare solutions, complemented by supporting services, that provide peace of mind to users.
Over 80 million connected devices deployed worldwide, Essence helps people to live safer and more independent lives.
Our electrical development team is looking for a highly capable Hardware Engineer with 6+ years of experience in board design and product development. The ideal candidate will take part in the design of new products as well as support and maintain existing products, working closely with cross-functional teams throughout the full development lifecycle.

Requirements:
B.Sc. in Electrical Engineering from a recognized university.
At least 6 years of hands-on experience in hardware development and board design.
Proven ability to leverage AI tools to support engineering workflows, including technical research, documentation, debugging, analysis, and productivity improvement.
Proven experience with battery-operated devices and low-power design.
Strong experience with microcontrollers.
Strong background in analog design and power supply circuits.
Experience with sensors, including analog and digital interfaces.
Experience with communication technologies such as LTE, USB, Wi-Fi, GNSS, and Ethernet.
Experience with communication interfaces and protocols such as SPI, UART, and I2C.
Experience in hardware debugging and HW/SW integration.
Hands-on experience with lab equipment such as oscilloscopes, spectrum analyzers

This position is open to all candidates.

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03/03/2026

Power Electronics Engineer

חברה חסויה

Location: Herzliya

Job Type: Full Time

Power the Future with us! we're a global leader in smart energy technology, with over 3,000 employees, offices in 34 countries, and millions of installations worldwide. Our innovative solutions include solar inverters, battery Storage, backup systems, EV charging, and AI-based energy management. We're committed to making clean, green energy the primary power source for homes, businesses, and beyond. With the growing demand for electricity, the need for smart, clean energy sources is constantly rising. we offer amazing opportunities to develop your skills in a multidisciplinary environment, covering everything from research and development to production and customer supply. Work with talented colleagues, tackle exciting challenges, and help create a sustainable future in an industry that's always evolving and innovating. Join us and be part of a company that values creativity, agility, and impactful work. Are you passionate about designing high-performance power systems that move from concept to mass production? Join us and take a leading role in shaping our next-generation flagship products! What Youll Do:
* Lead the end-to-end development of advanced power electronics hardware - from architecture and schematic design through validation and mass production.
* Own complex board-level designs, driving performance, reliability, and cost optimization.
* Design, simulate, build, TEST, debug, and bring to life robust power solutions under real-world constraints.
* Collaborate in a multidisciplinary R&D environment alongside Mechanical, Software, system, and Certification teams.
* Influence product architecture and technical direction with hands-on engineering excellence.
* Ensure on-time delivery of high-quality, production-ready designs. Why Join Us?
* Work on impactful, market-leading products.
* Be part of a highly collaborative, multidisciplinary engineering culture.
* Take real ownership and influence technical decisions.
* See your designs transition from concept to millions of units in the field.
Country:
Israel
City:
Herzliya

Requirements:
* B.Sc. in Electrical Engineering.
* 2+ years of hands-on experience in circuit and board design (power electronics preferred).
* Strong lab experience - Oscilloscope, Spectrum Analyzer, Electronic Loads, and other validation equipment.
* Experience with simulation tools such as LTspice, PSpice, MATLAB, or equivalent.
* Deep knowledge of analog design, LCR components, filters, and op-amps.
* Solid understanding of DC-DC converter topologies (Buck, Boost, Flyback, etc.).
* Experience with OrCAD (Allegro, Capture) or similar PCB design tools.
* Magnetic design and simulation experience - an advantage
* Background in control theory and experience working with microcontrollers - an advantage

This position is open to all candidates.

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26/03/2026

hw board design engineer

חברה חסויה

Location: Petah Tikva

Job Type: Full Time

we are looking for an experienced Hardware Design Engineer with a strong background in high-speed board design to join our radar hw group.
our imaging radar organization develops automotive radar systems that enable advanced driver assistance and fully autonomous driving. the radar hw group has multidisciplinary responsibilities and owns the end-to-end development of all radar hardware which includes: RF and high-speed digital boards, ic packages, mechanical solutions & antenna design
what will your job look like?
design high-speed boards from concept to production
own all design stages: architecture, schematics, layout, modeling, and design reviews
work on boards that include high-speed serdes, lpddr5/4, power circuits, and additional digital interfaces
collaborate closely with RF, mechanical and system teams.

Requirements:
all you need is:
b.sc. in electrical engineering
3+ years of experience in high-speed board design and simulation tools
knowledge with RF design
hands-on experience with orcad and allegro
solid understanding of high-speed digital and power integrity concepts
experience with si/pi modeling tools (e.g., hyperlynx, hfss, 3d designer, ads)
experience with ddr / lpddr and high speed serdes designs - advantage
We change the way we drive, from preventing accidents to semi and fully autonomous vehicles. if you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

This position is open to all candidates.

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31/03/2026

Senior Core Datapath Engineer

חברה חסויה

Location: Herzliya

Job Type: Full Time

In the Hybrid Cloud, Zerto drives the innovation agenda and technology roadmap for cutting-edge solutions in data lifecycle management, cyber resilience, replication, ransomware recovery, and seamless migrations. Our mission is to empower businesses with advanced hybrid cloud technologies that ensure data resilience, business continuity, and operational efficiency. With a focus on delivering state-of-the-art solutions, Zerto helps organizations protect, manage, and optimize their data across its entire lifecycle while maintaining robust defenses against evolving cyber threats. By working with customers, we help them reimagine their disaster recovery and data protection strategies, ensuring they achieve their business goals with confidence. Join us to redefine whats next in the hybrid cloud, data protection, and cyber resilience-and for yourself.

Roles and Responsibilities

Design, develop, and enhance I/O subsystems, virtualization, kernel programming, and memory management for cutting-edge system software products.
Drive performance optimization, and efficient memory management.
Perform in-depth debugging, triaging, and resolution of user and kernel-level, performance profiling, and memory-related issues.
Develop innovative solutions, addressing challenges in virtualization, multithreading, and hardware-software interaction.
Explore and implement new methodologies fostering continuous improvement and innovation.
Proactively identify bottlenecks in system design, and recommend and implement robust, scalable solutions.
Stay updated on evolving trends in kernel development, design, and virtualization technologies to bring innovative practices to the team.
Troubleshoot and optimize complex I/O and kernel features to enhance performance, scalability, and reliability.
Collaborate with cross-functional teams to align on design goals and ensure seamless integration with the system architecture.
Exhibit flexibility in taking on new or related tasks, showcasing adaptability and a proactive, problem-solving mindset.
Provide technical leadership in architecture design, problem-solving, and decision-making across complex technical domains.
Lead technical discussions, design reviews, and decisions on critical system challenges, driving the adoption of innovative solutions and best practices.

Requirements:
Qualifications:
Bachelors degree in Computer Engineering, Electronics, or Electrical Engineering.
Masters or PhD in a relevant domain is highly desirable.
10+ years of experience in product R&D within the computer/system software industry, focusing on kernel and driver development.

Knowledge and Skills:
In-depth working knowledge and Hands-on experience in I/O subsystems, programming, and kernel development.
Expertise in C and C++ programming languages.
Strong understanding of operating system internals and kernel & driver internals, including memory management, threading, and resource scheduling.
Proven expertise in debugging, kernel triaging, and resolving memory and performance-related issues.
Proficient in performance profiling, multithreading, and driver programming.
Strong Knowledge in Linux and virtualization technologies such as VMware, Hyper-v and KVM.
Ability to Design and implement scalable, efficient solutions for complex datapath and kernel challenges.
Strong ability to innovate and bring fresh approaches to technical challenges.
Excellent problem-solving skills with a proactive mindset and sharp analytical abilities.
Exceptional communication skills to effectively present and discuss technical designs, proposals, and solutions with senior management and stakeholders.
Demonstrated technical leadership with a focus on driving innovation.

Additional Skills:
Cloud Architectures, Cross Domain Knowledge, Design Thinking, Development Fundamentals, DevOps, Distributed Computing, Microservices Fluency, Full Stack Development, Release Management, Security-First Mindset, User Experience (UX).

This position is open to all candidates.

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26/03/2026

Cyber security architect

חברה חסויה

Location: Petah Tikva

Job Type: Full Time

our radar team develops cutting-edge radar technology for autonomous driving (av) and advanced driver-assistance systems (adas). we are looking for a Cyber security architect to lead the design and implementation of robust security solutions that protect our radar systems from cyber threats.
in this role, you will define security architecture for radar hardware, Embedded software, and communication interfaces, ensuring compliance with automotive cybersecurity standards and safeguarding mobileyes mission-critical sensing technology.
youll be part of a team shaping the future of autonomous driving. our radar technology is a critical component in delivering safe, reliable, and intelligent mobility solutions. youll work on innovative projects in a collaborative environment, with the opportunity to influence security strategy at a global scale. what will your job look like?
security architecture design - develop and maintain end-to-end security architecture for radar systems, including hardware, firmware, and software components.
threat modeling & risk assessment (tara) - perform threat analysis and risk assessment for radar components, software modules, and communication channels; identify vulnerabilities and design mitigation strategies.
secure communication - implement encryption, authentication, and integrity checks for radar data transmission between hardware and software layers.
secure software design - define and enforce security controls for apis, middleware, and integration points between radar systems and other vehicle subsystems.
compliance & standards - ensure radar systems meet iso 21434, unece wp.29, and other relevant automotive cybersecurity regulations.
collaboration with r&d - work closely with radar engineers, Embedded software developers, and system architects to embed security into the design process.
incident response support - provide architectural guidance during security incidents involving radar systems.
technology evaluation - assess and recommend security tools, frameworks, and methodologies for radar-specific applications.

Requirements:
all you need is:
b.sc. or m.sc. in Computer Science, electrical engineering, cybersecurity, or related field.
7+ years of experience in cybersecurity roles, with at least 3 years in architecture or senior design positions.
proven experience securing Embedded systems, hardware connections, software modules, and Real-Time communication protocols.
strong background in system architecture - ability to design and analyze complex, multi-component systems and ensure security is integrated at every layer.
strong knowledge of cryptography, secure boot, firmware integrity verification, and secure api design.
experience with automotive cybersecurity standards (iso 21434, unece wp.29).
understanding of can, ethernet, and automotive communication protocols.
excellent communication and documentation abilities.
strong problem-solving mindset and ability to work in cross-disciplinary teams.
experience in radar system development or RF engineering - advantage
knowledge of ai/ml security considerations - advantage
certifications such as CISSP, ccsp, or ceh - advantage mobileye changes the way we drive, from preventing accidents to semi and fully autonomous vehicles. if you are an excellent, bright, hands-on person with a passion to make a difference come to lead the revolution!

This position is open to all candidates.

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26/03/2026

senior chip design hardware emulation engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

looking for a best-in-class chip design - hw emulation senior engineer to join our outstanding networking silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! come and take a significant part in emulating our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company. join world-class emulation team in israel. our focused team takes switches/nics/socs designs and program the emulators to behave like our silicon. are you ready to take on interesting problems and craft solutions? come check out our team.
what you will be doing:
the main responsibility is emulation and prototyping of complex chip designs. this includes defining the methodology and crafting the infrastructure needed to quickly take large chips into hardware emulation platforms.
the job also requires close collaboration with design, verification, and software engineers to enable Embedded software and application software development.
connecting emulator/fpga based solutions to real external h/w or virtual targets, taking care of complex testbench and different protocols.
this is a role for a versatile engineer that includes rtl design, verification, fpga partitioning and implementation, scripting, and lab-based bring up of the design.

Requirements:
what we need to see:
bsc or msc in electrical engineering or Computer Science or equivalent experience
4+ years working in the semiconductor industry.
hands-on pre-silicon verification or design experience.
experience in building TEST -benches and debugging simulation failures.
experience in scripting with Python /tcl/ C / PERL / Unix shell
strong interpersonal skills and ability & desire to innovate.
ways to stand out from the crowd:
experience with hw emulation platforms.

This position is open to all candidates.

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26/03/2026

senior silicon dft lead

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as the design for TEST (dft) engineer lead, you will play a crucial role in dft architecture and dft design, and support devices to production. you will be responsible for providing technical leadership in dft, developing flows, automation, and methodology, planning dft activities, tracking the dft quality throughout the project life-cycle, and providing sign-off dft to tapeout.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
lead and execute dft activities in the design, implementation, and verification solutions for application-specific integrated circuits (asic).
develop dft strategy and architecture, including hierarchical dft, memory built-in self TEST (mbist), and automatic TEST pattern generation (atpg).
work with other engineering teams (e.g., design, verification, physical design) to ensure that dft requirements are met and mutual dependencies are managed.
manage a dft team planning, deliverables, and provide technical mentoring and guidance.
lead dft execution of a silicon project, planning, execution, tracking, quality, and signoff.

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, or a related field, or equivalent practical experience.
8 years of experience in design for TEST from dft architecture to post silicon production support.
4 years of experience with people management.
experience with dft design and verification for multiple projects, dft specification, definition, architecture, and insertion.
experience with dft techniques and common industry tools, dft and physical design flows, and dft verification flow.
experience in leading dft activities throughout the whole asic development flow.
preferred qualifications:
master's degree in electrical engineering or a related field.
experience in post-silicon debug, TEST or product engineering.
experience in jtag and ijtag protocols and architectures.
experience in SOC cycles, silicon bring-up, and silicon debug activities.
knowledge of fault modeling techniques.

This position is open to all candidates.

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26/03/2026

senior board design engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a hardware board design engineer, you will own the electrical design of complex high performance computing (hpc) systems. you will drive the development of next-generation ai accelerator boards, ensuring they meet signal integrity, power delivery, and thermal requirements. you will work cross-functionally with silicon (asic), signal integrity, power, mechanical, and manufacturing teams to bring products from concept to mass production.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer printed circuit boards (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (high bandwidth memory/ddr5).
design and validate high-speed interfaces including peripheral component interconnect express (pcie) gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering 1000a currents with fast transient response for ai processors.
work closely with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board. debug complex hardware issues using oscilloscopes, time-domain reflectometers (tdrs), and logic analyzers. root-cause failures to component, assembly, or design issues

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, or equivalent practical experience.
5 years of experience in board design (schematic and layout supervision) for server, networking, or high performance computing products.
experience in designing with serial interfaces (e.g., serdes, pcie, ethernet, ddr) and signal integrity (insertion loss, crosstalk, impedance matching).
preferred qualifications:
experience with dc-dc power converter design and power integrity concepts.
experience bringing up complex socs and debugging interaction between hardware, firmware, and software.
proficiency with electronic design automation (eda) tools (cadence concept/allegro, or similar).

This position is open to all candidates.

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26/03/2026

senior manager, software verification

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

seeking a dynamic and highly motivated senior Software manager to lead our software verification and automation for doca networking sdk. we are looking for a candidate who can excel in a sophisticated, multidisciplinary environment, take ownership, and drive high-quality verification and automation processes. this position offers the opportunity to have a real impact on sophisticated, groundbreaking products, delivered by nvidia and developed by our customers, empowering the most advanced data centers in the world. this role requires close collaboration with teams across various fields (sw, hw, QA ) to elevate our product to the next level.
what you'll be doing:
lead teams of software Verification engineers, providing technical direction, career development, and performance mentorship
define and continuously refine our software testing methodology and processes
engage in a hands-on approach, actively participating in the design, coding, and debugging of verification tests and infrastructure alongside your team
lead the verification process, ensuring the functionality, stability, and performance of our doca networking sdk and the solutions on top of it
work closely with internal and external customers to understand system use cases
analyze coverage measures to identify verification gaps and provide data -driven insights into product development and release readiness

Requirements:
what we need to see:
b.sc degree or equivalent experience in Computer Science, computer engineering, or electrical engineering
10+ years of overall professional experience and 4+ years of experience managing managers or senior engineers.
proficient in Python, C, C ++ with the technical depth to guide and mentor the team
experience with regression systems and their optimizations
experience with networking protocols, mainly ethernet
experience with virtualization technologies
strong analytical, debugging, and problem-solving skills with meticulous attention to detail
experience with Embedded sw development
excellent interpersonal skills and the ability to multitask in a dynamic environment with shifting priorities
self-motivated and well-organized
ways to stand out from the crowd:
advanced understanding in ethernet protocols and rdma
experience with cloud and ai workload optimization
proficiency in continuous integration (ci) methodologies and tools such as gerrit, jenkins, and gitlab
experienced in TEST generation and coverage methods and metrics
background in Linux Kernel, security protocols

This position is open to all candidates.

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26/03/2026

rtl design technical lead, networking, cloud

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as part of our server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will contribute in all phases of application-specific integrated circuit (asic) designs from design specification to production. you will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver high quality SOC /rtl. you will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.the ml, systems, & cloud ai (msca) organization at our company designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our company services (search, youtube, etc.) and our company cloud. our end users, cloud customers and the billions of people who use our company services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including our company clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the block level design documents such as interface protocol, block diagram, transaction flow, pipeline, and more.
perform rtl development (e.g., coding and debug in verilog, systemverilog, vhdl), function/performance simulation debug, and lint/cdc/fv/upf checks.
participate in synthesis, timing/power, and fpga/silicon bring-up.
participate in TEST plan and coverage analysis of the block and SOC -level verification.
communicate and work with multi-disciplined and multi-site teams.

Requirements:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, a related field, or equivalent practical experience.
10 years of experience architecting networking asics from specification to production.
8 years of experience in technical leadership.
experience in one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
experience developing rtl for asic subsystems.
preferred qualifications:
experience working with design networking like: remote direct memory access (rdma) or packet processing and system design principles for low latency, high throughput, security, and reliability.
experience in tcp, ip, ethernet, pcie and dram including network on chip ( NOC ) principles and protocols (axi, ace, and chi).
experience architecting networking switches, end points, and hardware offloads.
understanding of packet classification, processing, queuing, scheduling, switching, routing, traffic conditioning, and telemetry.

This position is open to all candidates.

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8592921

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אירעה שגיאה בשליחת פרטיך למשרה

26/03/2026

design technology co-optimization engineer

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

about the job
in this role, youll work to shape the future of ai/ml hardware acceleration. you will have an opportunity to drive cutting-edge tpu (tensor processing unit) technology that powers google's most demanding ai/ml applications. youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of google's tpu. you'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on tpu architecture and its integration within ai/ml-driven systems.
as a design technology co-optimization (dtco) engineer, you will bridge the gap between process technology and product architecture to define the next generation of datacenter-class silicon. you will be responsible for extracting maximum process entitlement by evaluating advanced logic nodes and emerging transistor architectures.in this role, you will conduct place and route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. you will collaborate with foundry, ip, and architecture teams to identify power, performance, and area (ppa) bottlenecks and drive system technology co-optimization (stco) initiatives.your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify ppa gains. by navigating the trade-offs between process complexity and design performance, you will ensure googles hardware achieves efficiency and power density.the ai and infrastructure team is redefining whats possible. we empower google customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include googlers, google cloud customers, and billions of google users worldwide. we're the driving force behind google's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for google cloud, google global networking, data center operations, systems research, and much more.
responsibilities
execute high-fidelity place and route experiments to evaluate the ppa impact of advanced process features, library architectures, and design rule variations on datacenter-class ip.
drive design technology co-optimization by collaborating with foundries and internal technology teams to define optimal metal stacks, track he

דרישות:
minimum qualifications:
bachelor's degree in electrical engineering, computer engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in physical design (rtl-to-gds) or technology development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
experience with industry-standard place and route (p&r) tools and static timing analysis (sta) tools.
experience in cmos device physics, finfet/nanosheet architectures, and the impact of layout parasitics on ppa.
experience in scripting and automation using tcl and Python (or PERL ) to manage design sweeps and data extraction.
preferred qualifications:
master's degree or phd in electrical engineering, computer engineering or Computer Science, with an emphasis on computer architecture.
experience in design technology co-optimization (dtco), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
experience working with major foundry technology files (pdks) and interpreting design rule manuals (drm) to guide physical im המשרה מיועדת לנשים ולגברים כאחד.

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