We are looking for a System Engineer Team Lead to lead our next generation system development.
In this role, the Project Lead will technically lead a complex multidisciplinary electro-optical system architecture. He will define and manage the required performance analysis, technical solutions, implementation methods, and field deployment to the customer's satisfaction.
Responsibilities
What you will be doing:
Technical:
Design the system architecture/high-level design and technical requirements.
Serve as the system go-to person for all technical matters; a technical expert knowledgeable in system operation, performance, and troubleshooting. Act as the technical POC for system escalations and customer support.
Project Management:
Plan, monitor, and lead the project to ensure product delivery within required specifications, on time, and within the allocated budget (Gates, PMR).
Maintain a project risk management and mitigation plan.
Lead the development activities and technical reviews throughout the PLC (SRR, PDR, CDR, FDR) and other technical design reviews.
Assign project tasks, follow up, and align with development groups, service, and production.
Lead all aspects of the beta tool delivery.
Act as the key contact for inbound topics (matrix interface) and outbound topics with MKT.
Team:
Develop and grow team ownership and technical capabilities.
Provide technical guidance for System/Product engineers.

Be part of a dynamic and motivated multi-national Physical Design team, taking part in developing a state-of-the-art Satellite SoC through the full life cycle: design to production. The chips include complex digital and analog modules. Some of the products are part of the next generation radiation hardened satellite modems. You will have access to best-in-class EDA design tools and will be working in leading edge process technologies.

Responsibilities

Physical implementation of complex SoC, VLSI devices and Test Chips, integrating custom designs and 3rd party IP (Hard, Soft, IO, CPUs, DSPs, etc)
Full block level timing closure and manufacturing checks signoff including power planning and analysis
Working alongside the Logic Design RTL team to develop timing constraints for implementation at block and chip level
Insertion of DFT test structures and chip level integration, capture and simulation
Jointly with management, build your career development and growth opportunities.