in this role, you will help build socs by driving quality and reliability processes from the integrated circuit (ic) perspective. working with various cross-functional teams, you will develop quality and reliability specifications, develop and deploy design guidelines, and develop and execute TEST plans. within the larger organization, you will collaborate with global hardware quality and reliability, silicon design, validation, and engineering teams. you will have an understanding of ic flows, wafer processing, testing, qualification, yield, reliability, and failure analysis.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define and lead qualification hardware and TEST developments in front of internal teams and external vendors.
define and execute silicon and package qualification activities (e.g., htol, elfr, esd/lu, b/hast, thb, etc.).
extract, manipulate, and analyze large volumes of data from silicon and package qualification programs (e.g., htol, elfr, esd, lu, uhast, tct, etc.), high volume mfg, and field returns to identify failure mechanisms, reliability trends, and opportunities for yield, quality, and reliability improvement.
own cross-functional investigation of ic quality and reliability issues to identify root causes and develop solutions (e.g., rma triage, analytics, failure analysis, etc.).
develop and implement physics-based statistical quality and reliability models (e.g., elf, tddb, nbti, hci, time zero failures, etc.) to predict silicon device failure mechanisms, degradation patterns, and lifetime behaviors.

we are looking for an excellent virtual platform fw engineer to join the infrastructure and simulation integration group. in this role, you will integrate a systemc/tlm virtual hardware platform (delivered by the hardware modeling team) with firmware, make the end to end flow run reliably, and turn it into a productive environment for early development and regressions. with many hardworking engineers around the globe, the work environment is complex, driven by a passion for achieving goals, and fast paced. you will learn how large scale firmware projects are operated, maintained, qualified and released, and how firmware and pre-silicon platforms are developed together to accelerate product readiness.
what you will be doing:
work closely with firmware, hardware architecture, systemc modeling, and build/tools teams.
integrate firmware images with a systemc/tlm virtual platform and enable end to end boot, bringup, and feature flows.
define and implement hw-fw interfaces for the virtual platform (mmio, interrupts, dma, boot flows, configuration).
integrate the virtual platform flow into ci, regressions, and nightly qualification, including triage and failure analysis.
drive stability, scalability, and performance of virtual platform runs and regressions.
document processes, guidelines, and tooling that make the virtual platform easy to adopt across teams.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a design team manager within the server chip design team, you will use your asic design experience to be part of a team that creates the SOC vlsi design cycle from start to finish. you will collaborate closely with design and Verification engineers in active projects, creating architecture definitions with rtl coding, and running block level simulations.in this role, you will oversee the intellectual property (ip) and SOC vlsi design cycle from architecture to production. you will own and manage ip, subsystems and SOC development, leading a group of designers and design tech leads. you will be responsible for mentoring and developing team members and tech leads, driving improvements in leadership, technical execution, and design flows.the ai and infrastructure team is redefining whats possible. we empower our customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our cloud, global networking, data center operations, systems research, and much more.
responsibilities
manage a team of tech leads and designers. develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
lead design activities at ips, subsystems, and system -on-chips (socs).
plan, execute, track progress, assure quality, and report status of the assigned activity.
work closely with internal customers and support multiple activities and deliverables.
assure and manage deliverables quality at all rtl design categories including reviews, static checks, design for physical design, power, etc.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a cpu workload analysis researcher within our company cloud's msca organization, you will be integral to developing silicon solutions powering our company's direct-to-consumer products. you will join a research and development team focused on analyzing and profiling workloads requirements within the company cloud environment. your role will involve conducting in-depth research on cpu optimization, feature development, and ml usages over compute platforms, contributing to identifying key areas of investment and future opportunities. this role offers a unique opportunity to perform groundbreaking research with a significant impact on both research methodologies and industry products, within the server chip architecture team. your work will directly influence the next generation of hardware experiences for millions of our company users and cloud customers.the ai and infrastructure team is redefining whats possible. we empower our company customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers, our company cloud customers, and billions of our company users worldwide. we're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for our company cloud, our company global networking, data center operations, systems research, and much more.
responsibilities
plan and execute detailed analysis of cpu workloads within the company cloud infrastructure, analyze trends and map future requirements.
collaborate closely with architecture and modeling owners to understand design specifications and identify critical scenarios related to cpu performance and efficiency.
develop and implement custom workload generation tools and methodologies to simulate real-world usage patterns on our company cloud platforms.
analyze the impact of Machine Learning applications on cpu usage, identifying opportunities for optimization and feature enhancements.
lead the investigation and development of metrics to measure cpu performance and efficiency, presenting findings to stakeholders and contributing to strategic decisions.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
in this role, you will use application-specific integrated circuit (asic) design experience to be part of a team that develops complex asic system -on-chip ( SOC ) intellectual property from proof-of-concept to production. this includes creating ip level microarchitecture definitions, register-transfer level (rtl) coding and all rtl quality checks. you will also have the opportunity to contribute to design flow and methodologies, including design generation automation. you will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. you will develop/define design options for performance, power and area.the ml, systems, & cloud ai (msca) organization at our designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all our services (search, youtube, etc.) and cloud. our end users are, cloud customers and the billions of people who use services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
define the ip microarchitecture level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
perform rtl development (coding and debug in verilog, systemverilog).
conduct function/performance simulation debug and lint/cdc/fv/upf checks.
engage in synthesis, timing/power closure, and asic silicon bring-up.
contribute to verification TEST plan and coverage analysis of block and SOC -level.

be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
as a SOC physical design engineer, you will collaborate with functional design, design for testing (dft), architecture, and packaging engineers. additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind.the ai and infrastructure team is redefining whats possible. we empower customers with breakthrough capabilities and insights by delivering ai and infrastructure at unparalleled scale, efficiency, reliability and velocity. our customers include , cloud customers, and billions of our  users worldwide. we're the driving team behind our groundbreaking innovations, empowering the development of our cutting-edge ai models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. from software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our tpus, vertex ai for cloud, global networking, data center operations, systems research, and much more.
responsibilities
define and drive the implementation of physical design methodologies.
take ownership of one or more physical design partitions or top level.
drive to the closure of timing and power consumption of the design.
contribute to design methodology, libraries, and code review.
define the physical design related rule sets for the functional design engineers.

We are seeking an experienced and highly motivated Firmware Engineer to join our NIC/Switch Firmware Development Team in Tel Aviv.

The successful candidate will design and develop innovative firmware features to unleash the full potential of our ConnectX/Switch architecture.
Our Firmware Team develops cutting-edge networking features for cloud, HPC, and storage.

This position requires a broad background in NIC or Switch architecture, along with a proven ability to develop robust and efficient solutions to complex design challenges.

The Firmware Team drives the data growth of the worlds largest companies. With talented engineers around the globe, our work environment is dynamic and meaningful.

What You Will Be Doing:
Deepen Your Expertise: Gain a thorough understanding of system debugging, networking technology and stacks, as well as the HW/FW/SW relationships.
Innovate Firmware Features: Design and implement new firmware features in our NIC/Switch Firmware core (e.g., our ConnectX/Spectrum products).
Optimize Performance: Characterize and refine key firmware design elements and code to maximize performance and ensure robustness and flexibility.
Learn Complex Project Management: Understand how a large, complex software project is operated, maintained, qualified, and released, and learn how hardware and firmware are developed.

Founded in Tel Aviv in 2016, UVeye is a computer vision and data company that creates automatic vehicle inspection systems to encourage road safety and increase transparency across the automotive industry. With key partnerships including General Motors, Volvo, and CarMax among others, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more.
With over $380M in funding and strategic partnerships with industry giants such as Toyota, Amazon, General Motors, Volvo, and Hertz, our technology is utilized in manufacturing plants, dealerships, wholesale auctions, delivery fleets, security checkpoints, and more. Our growing global team of over 250 employees is committed to creating a workplace that celebrates diversity, encourages teamwork, and strives for excellence.
UVeye is looking for an experienced Electronics Engineer to join our growing R&D Hardware team and lead and deliver Hardware projects.
Here’s what you’ll be doing:
* Develop and own all electrical modules for UVeye products.
* Integrate new components and sensors into the system.
* Perform PCB development activities for new and improving the existing.
* Lead troubleshoots of faulty electrical components.
* Cooperate with the system engineer, mechanics, and SW teams to develop next-gen features and products.

our company is searching for a strong technical leader to own the backbone of our networking research capabilities. we are looking for an engineering manager to lead the development of our high-fidelity network simulation platform and the extensive on-premise infrastructure that powers it.
in this role, you will lead a team of performance simulation software engineers and DevOps /infrastructure specialists. you will own the "simulation-as-a-service" product-a critical platform used by internal researchers to model next-generation data center architectures. your mission is to ensure our simulations are accurate, performant, and accessible, while managing the large-scale compute clusters required to run them.
what you'll be doing:
team leadership: manage and mentor a team of C ++ software engineers and DevOps infrastructure engineers, fostering a culture of performance, reliability, and code quality.
product ownership (sim-as-a-service): treat the internal simulation platform as a product. work with research partners to define the roadmap, prioritize features, and ensure high availability for users.
high-performance simulation: be responsible for the architecture and optimization of complex network simulation engines ( C ++ based), ensuring they can scale to model extensive data center topologies with high fidelity.
infrastructure management: own the lifecycle of our on-premise compute clusters and servers. drive decisions on hardware upgrades, prioritisation, and managing system resources.
DevOps & automation: lead the strategy for ci/cd pipelines, automated testing, and containerized deployments to ensure rapid iteration and stability of the simulation platform.
multi-functional collaboration: partner with the ai agents team to expose simulation apis, enabling agents to run experiments and gather data autonomously.

about the job
be part of a team that pushes boundaries, developing custom silicon solutions that power the future of direct-to-consumer products. you'll contribute to the innovation behind products loved by millions worldwide. your expertise will shape the next-generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.the ml, systems, & cloud ai (msca) organization at google designs, implements, and manages the hardware, software, Machine Learning, and systems infrastructure for all google services (search, youtube, etc.) and google cloud. our end users are googlers, cloud customers and the billions of people who use google services around the world. we prioritize security, efficiency, and reliability across everything we do - from developing our latest tpus to running a global network, while driving towards shaping the future of hyperscale computing. our global impact spans software and hardware, including google clouds vertex ai, the leading ai platform for bringing gemini models to enterprise customers.
responsibilities
lead the schematic capture and component selection for high-density, multi-layer pcbs (20+ layers) incorporating high-power asics (tpus/cpus), fpgas, and high-speed memory (hbm/ddr5).
design and validate high-speed interfaces including pcie gen 6.0/7.0, 400g/800g/1.6t ethernet (pam4). collaborate with signal integrity (si) engineers to define routing constraints and stack-up.
design multi-phase power regulators (vrms) capable of delivering >1000a currents with fast transient response for ai processors.
work with pcb layout designers to guide placement and routing of critical signals and power planes.
lead the lab bring-up of first-silicon/first-board by debugging hardware issues using oscilloscopes, tdrs, and logic analyzers to root-cause failures to component, assembly, or design issues.