As Chief Engineer, you will be responsible for ensuring that all electrical, mechanical, and fire/life safety equipment within the data center is operating at peak efficiency. This involves planned preventative maintenance of equipment, daily corrective work, and emergency response. You are expected to be a singular focal point for all facility operations and to support Amazon within its owned and operated data centers.

You should be able to manage large scale impacting projects and new region support from conception to completion. These projects involve large amounts of independent work as well as collaboration with external support groups including engineering, automation, procurement, and finance in both local and global settings. As Chief Engineer, you will be tasked with creating and delivering on key milestones, obtaining and tracking quotes for all necessary costs, and documenting project results for future implementation at other facilities. The goals of such projects are for the Chief Engineers to drive innovation and resiliency while reducing operational costs in the facilities.

Key job responsibilities:
Train and support the Engineering team in their role of providing electrical and mechanical equipment troubleshooting and operations.
Implement and execute site or equipment-specific training exercises. Exercises cover, but are not limited to: stand-by diesel generators, switchgear, UPSs, PDUs, AHUs, chillers etc.
Oversee day-to-day operation and maintenance of mechanical and electrical equipment in data center sites.
Operate independently, with limited direct management.
Assist in the design and build-out of new facilities and perform root cause analysis of equipment failures.
Act as an escalation point for all facilities-related issues within the data center region. Work OT hours as needed to support site stability.
Troubleshoot and report facility and data sever-level events within internal Service Level Agreements (SLA).
Create and deploy standard practices for Engineering Operations Technicians, Chief Engineers, and vendor support teams.
Ensure all safety procedures are adhered to by vendors, and AWS staff.

At our company, we understand transport networks and what moves people. From high-speed trains, metros, monorails, and trams, to turnkey systems, services, infrastructure, signalling and digital mobility, we offer our diverse customers the broadest portfolio in the industry. Every day, more than 80 000 colleagues lead the way to greener and smarter mobility worldwide, connecting cities as we reduce carbon and replace cars.
PURPOSE OF THE JOB:
As a Power Supply Automation Engineer, you will be responsible for both basic and detailed design within the Substation Automation scope and the emergency cut-off system of railway transportation infrastructure electrical power stations. This includes systems for traction, intake, and distribution substations, focusing on remote control and monitoring, substation-level communication, and interface with SCADA and other systems. You will implement the latest standards and technologies, such as: IEC 61850 client-server communications, GOOSE messaging, Fiber optic networks, IEC 104 and OPC UA communication protocols when required by the project. Additionally, you will coordinate with Cyber Security experts and ensure the implementation of a cyber-security compliant solution tailored to the project's needs.
MAIN RESPONSABILITIES :
Key Accountabilities:
Prepare and execute testing activities
in support to one or several Projects on railway Power supply Automation systems under the direction of his / her hierarchy
according to the testing procedure / documentation and following POS T&C Leader and / or PrCOM instructions
Ensure defects identification and correction (trouble shooting)
In the event of a non-conformity observed during the commissioning phase, make a return experience (REX) towards the project, and ensure that all design related issues are correctly reported in the adequate tools, including the defect description and associated test context
Ensure follow-up of detected issues and deliver the commissioning reports.
Check that the test tools are in perfect working order and calibrated.
Support V&V team and perform test in lab as per request
Deliver the committed performance in terms of Quality, Costs and Deadlines and in compliance with our company policies, local standards and regulations (in particular EHS and Railway Safety)
Prepare SAT, and site test procedures; execute tests and manage punch lists.
validate PLC/HMI logic and SCADA integration.
Support live energization and troubleshoot issues.
Maintain automation configuration and ensure QCD and DFQ compliance.

our company's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets our company's standards of quality and reliability.
As a Senior SoC System Test Engineer, you will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization, and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will work with various groups to deploy screening methodologies and flows for data processing, analytics, and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Collaborate with Architecture, Design and Verification teams to develop new product bring-up, validation, characterization, qualification strategies, and manufacturing test solutions for new High Performance Computing (HPC) products in advanced process technologies.
Validate test solutions on system-level platforms and prepare for mass production.
Work with hardware and software teams to evaluate functional device yield and performance across various operating conditions.
Develop effective production screens to reduce Defective Parts per Million (DPPM).
Assess test escapees and localize failures, implement containment measures in the manufacturing test flow, and partner with manufacturing, test, quality and reliability teams to identify root cause and implement corrective actions.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Performance Modeling Manager, you will lead a team of high-performing engineers responsible for the software performance models that are used to guide the future of our companys custom silicon. You will bridge the gap between software architecture and hardware implementation, ensuring that our next-generation CPUs and NICs are optimized for our companys most critical workloads, such as Gemini, Search, and Cloud AI.
In this role, you will lead a team of high-performing engineers in the development of sophisticated performance models and oversee the conduct of deep-dive architectural analyses. By guiding the team to explore various architectural alternatives under different scenarios, you will ensure the identification of bottlenecks and provide data-driven guidance to architects on preferred hardware implementations. Your focus will be on leading the technical roadmap and career development while maintaining high-level architectural influence across both CPU and NIC modeling domains.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving channel behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Build, lead, and mentor a team of performance modeling engineers, fostering a culture of technical excellence and innovation in the Tel Aviv and Haifa silicon space.
Define the goal for performance modeling tools and methodologies, ensuring they provide highly accurate projections for future architectural pivots.
Partner with Hardware Architects, Silicon Designers, and Software Workload teams to influence SoC specifications based on data-driven modeling results.
Drive the development of advanced SystemC performance simulators and infrastructure, ensuring scalability and correlation with post-silicon performance.
Serve as a subject matter expert in CPU/NIC micro-architecture, guiding the team through complex trade-off analyses (power, area, performance).

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout.The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC).
Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), and Automatic Test Pattern Generation (ATPG).
Work with other Engineering teams (e.g., Design, Verification, Physical Design) to ensure that DFT requirements are met and mutual dependencies are managed.
Manage a DFT team planning, deliverables, and provide technical mentoring and guidance.
Lead DFT execution of a silicon project, planning, execution, tracking, quality, and signoff.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design Team Manager within the Server Chip Design team, you will oversee the IP and SoC VLSI design cycle from architecture to production. In this role, you will own and manage IP, subsystems and SoC development, leading a group of designers and design tech leads.
You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead design activities at IPs, subsystems, and SoC.
Plan, execute, track progress, assure quality, and report status of the assigned activity.
Work closely with internal customers and support multiple activities and deliverables.
Assure and manage deliverables quality at all RTL design categories including reviews, static checks, design for physical design, power, etc.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As part of our Server Chip Design team, you will use your ASIC design experience to be part of a team that creates the SoC VLSI design cycle from start to finish. You will collaborate closely with design and verification engineers in active projects, creating architecture definitions with RTL coding, and running block level simulations.
As a Design & Power Methodology Team Manager within the Server Chip Design team, you will be responsible of managing and leading design and power methodologies from IP to SoC, pre and post silicon. You will be responsible for mentoring and developing team members and tech leads while driving improvements in leadership, technical execution, and design flows.
You will work closely with CAD vendors and internal teams to develop lead design and power methodology and execution.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Manage a team of tech leads and designers. Develop and mentor team members, and communicate and co-work with multi-disciplined and multi-site teams.
Lead flow and methodology development and assimilation across multiple groups. Work closely with CAD tool providers as well as internal CAD teams.
Plan, execute, track progress, assure quality, and report status.
Work closely with internal customers and support multiple activities and deliverables.
Drive design methodologies such as design construction, CDC, RDC, SDC. Drive power at: IP and SoC RTL/Gate Level Optimization, estimation, correlation.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners.The ML, Systems, and Cloud AI (MSCA) organization at our company designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all our company services (Search, YouTube, etc.) and our company Cloud. Our end users, Cloud customers and the billions of people who use our company services around the world.
We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including our company Clouds Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.
Responsibilities
Generate precise electrical models (e.g., S-parameters, SPICE models) for components such as packages, PCBs, and connectors for use in simulations.
Simulate high speed interface electrical behavior using HSPICE or other circuit simulators.
Execute lab measurements utilizing test equipment like oscilloscopes, Vector Network Analyzers (VNA), Time Domain Reflectometers (TDR) , Spectrum analyzers to validate simulation outcomes and debug signal and power-related issues on silicon prototypes and boards.
Establish design rules and guidelines for optimal signal/power integrity during PCB and package layout, ensuring high production yield and reliability.
Document design specifications, analysis results, and validation reports to ensure compliance with standards and for future reference, while collaborating extensively with cross-functional teams, including ASIC architects, digital/analog designers, physical design/layout engineers, and system engineers.

We are looking for a creative and experienced Senior Firmware Engineer to join our PCIe Firmware team-someone passionate about using artificial intelligence to engineer the foundational hardware of the AI revolution.

As an integral part of our team, you'll architect and implement the core of our next-generation devices. This senior role places you at the center of innovation, where you will have a direct impact on our business and technology by solving sophisticated technical challenges. Its a unique opportunity to shape our technology and empower customers to build the supercomputers and AI fabrics of tomorrow.

What You'll Be Doing:
Lead the architectural design, development, and optimization of cutting-edge PCIe firmware, using AI-driven modeling and insights to deliver exceptional performance.

Serve as a trusted technical expert by investigating, debugging, and resolving challenging PCIe firmware issues for our most important customers.

Collaborate closely with our Chip Design, Verification, Software, and Architecture engineers to find root causes and develop robust, long-term solutions.

Champion the integration of AI-assisted diagnostics and generative AI tools across the entire development lifecycle to boost team productivity and innovation.

Translate customer needs and field data into actionable feedback that directly shapes the future of our products.

At our company, we understand transport networks and what moves people. From high-speed trains, metros, monorails, and trams, to turnkey systems, services, infrastructure, signalling and digital mobility, we offer our diverse customers the broadest portfolio in the industry. Every day, more than 80 000 colleagues lead the way to greener and smarter mobility worldwide, connecting cities as we reduce carbon and replace cars.
Main Responsabilities
Key accountabilities
Implementation of the necessary organization of one work front to enable the delivery, erection, installation works achievement in the optimal conditions: performances, costs, quality and health and safety.
The POS Installation Supervisor reports directly to the POS Installation Manager and is in charge of making sure that the power supply equipment is installed in conformity with the Basic and Detail Designs, the installation procedures, the Quality Assurance / Quality Control (QA/QC) system and the Time Schedule in place.
Its duties include also the necessity to report on all technical Issue: with the Engineering Manager and its Installation Manager about Detail Design concerns and with the procurement teams and its Installation Manager about Non-Conformities Reports (NCR) on equipment / material.
The POS Installation Supervisor had to prepare the 4M process before starting activities and had to submit it to the Installation Manager for starting GO decision.
During the Installation, the POS Installation Supervisor is required to organize the tasks, in a competent and consistent way, so that all key activities are properly controlled. He will coordinate with other contractors site teams.
The POS Installation Supervisor will manage and control the Subcontractors technical performance as per their subcontracting obligations.
The POS Installation Supervisor collects and signs the teams reports - Daily / Weekly -
Its duties include also to coordinate with OPC and other third parties on Site.
The POS Installation Supervisor is responsible of the teams & subcontractors works in compliance with our company EHS and local rules.
Its duties include the follow up of the service of the machine and maintain the highest level of availability.
The POS Installation Supervisor alerts and reports to the management on any concerns he has related to the job he has to perform, and especially regarding: EHS, Quality, Access, etc.
The POS Installation Supervisor is responsible for the onsite Quality Plan & EHS Plan implementation.
Delivery
Daily / Weekly progress report
Weekly Quality report based on the NCR analysis and the Quality controls reports
Weekly Hourly report of his Construction team.
Warehouse request
Analysis of the equipment or material consumption.
Report of the service of machines & tools
The POS Installation Supervisor must be based on-shore, on site, typically in the Project Leading Unit.
Performance measurements
Weekly works progress program control and associated reports.
Client complaints follow-up (non-conformity forms)
Quality Control indicators (Time to close NCR - OTD reception document)
On Time Delivery (OTD) Installation milestones
EHS indicators.