As a Graph Compiler Software Manager, you will lead the development of next-generation graph compiler technology. This compiler is a cornerstone of AI software offering, empowering customers to optimize, map, and execute complex neural networks across architectures with extraordinary efficiency. You will lead a group of talented engineers and team leaders working across domains such as compiler optimizations, graph-level transformations, operator mapping, scheduling, and code generation. We are seeking a visionary and technically strong leader with passion for excellence and impact in one of the most fascinating areas of AI and deep learning.

Key Responsibilities:

Lead the design and implementation of innovative graph compilation flows for AI workloads, from high-level optimizations to hardware-specific backends. Build and guide a strong, innovative, and results-driven compiler team that thrives on solving complex technical challenges. Collaborate with hardware architecture, VLSI, and software framework teams worldwide to ensure seamless integration and maximum performance. Lead the end-to-end delivery of graph compiler components while meeting aggressive KPIs. Establish and execute group planning processes to ensure timely and high-quality delivery. Provide technical and managerial guidance to team leaders and engineers. Define and drive compiler optimization strategies for AI and deep learning workloads.

The AI Graph Compiler Engineer will design and develop next-generation graph compiler technologies enabling efficient execution of advanced AI models on Neural Processing Units (NPUs) used in edge and embedded AI devices. In this role, you will work at the intersection of AI frameworks, graph optimization, and hardware acceleration, enabling efficient execution of neural networks on cutting-edge AI hardware.

You will work at the intersection of AI frameworks, compiler infrastructure, and hardware acceleration, helping translate high-level AI models into highly optimized executions on NPUs.



What will you do:

Develop and enhance AI graph compiler components targeting NPU architectures. Implement graph-level optimizations such as operator fusion, scheduling, memory planning, and layout transformations. Participate in lowering models from AI frameworks (e.g., PyTorch, ONNX, TensorFlow) into NPU-optimized representations. Contribute to compiler passes focused on performance, memory efficiency, and numerical correctness. Collaborate closely with hardware, runtime, and AI framework teams to achieve optimal end-to-end performance. Analyze performance bottlenecks and assist in compiler-based optimizations. Debug and resolve issues across compiler, runtime, and hardware layers. Support testing, validation, and documentation of compiler features.

We are seeking a highly motivated High-Performance System Architect to join our team of experts and help shape the future of high-performance and ML / AI computing. Our next-generation NVL systems will be at the forefront of connecting and powering the world's most advanced compute clusters, which would be used to train the most advanced AI models such as GPT and DeepSeek. As a high-performance system architect, you will have the opportunity to work on some of the most cutting-edge technology and help to drive the innovation of our next generation networks that will be used by top researchers and engineers around the world.

What youll be doing:
Define the NVL system architecture end-to-end, by internal requirements and customers requirements through all product life cycles (post/pre silicon, on deployments).
Research various of solutions to enable the next large-scale-high-performance computing clusters. The position spans over various layers from algorithms, software, firmware, and HW.
Collaborate with cross-functional teams, including other architecture teams, logic design, system software, firmware, and research teams, to ensure the successful execution of the project.

In this role, you will be a key contributor to the design and implementation of AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.

You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of NPU embedded solutions, actively promoting AI capabilities to the customers.

What will you do:

Own and design key components of the AI Graph Compiler software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.

We are now looking for Hardware Senior Manager for our Hardware Switch Group! The team leads the development of networking infrastructure for our next-generation data centers focusing on accelerated performance while enabling optimized end to end GPU connectivity. As a leader to our Hardware Engineering team, you'll guide, encourage, and drive a team of highly knowledgeable hardware engineers, providing them with interesting and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.

What you'll be doing:
Build the best team to implement and executing high-performance systems
A key member of team technical management team developing world-class switch designs
Lead Pioneering Switch System design from concept to mass production
Collaborate and integrate with all HW project disciplines: Board Design, Mechanics, Thermal, PCB Layout, Production, Software/Firmware, RTL and more
Planning the work of your team on multiple simultaneous development projects with a broader leadership team
Managing direct reports, goal setting, coaching, performance appraisals, career planning and compensation recommendations
Schedule projects, make realistic estimates of outcomes and work to make projects timely and successful for high volume manufacture.
This position is very hands-on and will require you to be intimately familiar with the entire design flow. From a technical standpoint, you will be hands-on and driving the engineering teams working the following parts of the project: specification definitions, electrical schematics, component selection, layout guidance, hands-on testing in a lab environment, accompanying production and qualification processes, micro-architecture, verification, characterization, design for testability, cost ,reliability and more.

The team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance while enabling optimized end-to-end GPU connectivity, focusing on datacenter-level optimized solutions for AI.

As a leader of our CPO switch Hardware Engineering team, you'll guide, encourage, and drive a team of highly skilled hardware engineers, providing them with stimulating and ambitious assignments and enabling them to stay creative and motivated while delivering products on schedule.

What You'll Be Doing:
Build the best team to design and execute high-performance CPO (Co Package Optics) switch system from concept to mass production.
Be a key member of the technical leadership team developing world-class CPO switch designs.
This position is hands-on and will require a deep understanding of all technical/engineering aspects of the project with intimate familiarity with the entire development flow. From a technical standpoint, you will lead and support engineering teams in the following areas: specification definition, electrical schematics, opto-mechanical design, component selection, layout guidance, hands-on lab testing, production processes, qualification workflows, micro-architecture development, verification, characterization, design for testability, cost optimization, reliability, and more.
Collaborate with and integrate all HW project disciplines: Board Design, Assembly Process, Mechanics, Thermal, PCB Layout, Process, Production Engineering, Software/Firmware, Procurement, NPI, and more.
Plan and oversee your teams work on multiple simultaneous development projects in coordination with the broader leadership team. Manage direct reports, set goals, provide coaching, conduct performance appraisals, plan careers, and make compensation recommendations.
Collect, examine, and filter requirements from internal customers such as marketing, software, and systems engineering to assemble a comprehensive plan of record for next-generation switches while planning resource allocation for projects and assign team members effectively.
Schedule projects, create realistic outcome estimates, and drive timely, successful execution for high-volume manufacturing.

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology.

Define of hardware and system architectures.

Research and evaluate algorithms currently used in related applications.

Develop complex proof-of-concepts to demonstrate ideas.

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

We are currently seeking a hard-working Senior System and Hardware TimeSync Architect who flourishes with these types of challenges to join our Time Synchronization Architecture team.

In this role, you will be exposed to the newest technologies and will help define how our GPUs, CPUs, and networking devices use timing to power extraordinary products and applications. Specifically, you will focus on next-generation Radio Access Network (RAN) platforms for 5G and 6G, delivering innovative, scalable, and power-efficient TimeSync solutions. By working across hardware and software stacks, you will support sophisticated AI acceleration and drive industry-wide standardization. If you want to lead the industry and help us define the next generation of data center and telecommunications technology, this is where you belong.

What youll be doing:

Master our Time Synchronization Technology

Define of hardware and system architectures

Research and evaluate algorithms currently used in related applications

Develop complex proof-of-concepts to demonstrate ideas

Architect Time Synchronization hardware tailored to the requirements of next generation RAN workloads, including distributed, centralized, and small cell deployment scenarios.

Collaborate with software architects to define new features and robust SW-HW interfaces for diverse networking use cases.

Drive standardization and interoperability to support broad industry adoption.

Own and design key components of the Edge AI software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.

We are looking for a visionary Senior System Architect to lead the charge in defining how we move data at speeds the world has never seen. We want to bridge the gap between silicon and the rack, ensuring our NVLink and InfiniBand fabrics remain the gold standard for performance. This is a chance to join a team where we don't just follow industry standards-we set them!

You will work at the intersection of Signal Integrity (SI), Mechanical Engineering, and System Protocol design to ensure that our NVLink and InfiniBand/Ethernet fabrics scale to terabit-per-second speeds with industry-leading power efficiency and reliability.

What Youll Be Doing:

Architectural Definition: Lead the end-to-end definition of high-speed interconnect systems for next-gen AI platforms (e.g., Rubin and beyond), focusing on 224G/448G PAM4 lanes and beyond.

Technology Roadmap: Evaluate and select pioneering technologies such as Co-Packaged Optics (CPO), Silicon Photonics, and advanced OSFP/QSFP-DD form factors.

System Co-Design: Collaborate with ASIC, Thermal, and PCB teams to optimize the "Silicon-to-Connector" path, minimizing insertion loss and improving signal integrity.

Standardization Leadership: Represent us in industry standards bodies (e.g., IEEE 802.3, OCP, MSA) to influence the future of high-speed connector and cable specifications.

Vendor Ecosystem: Work with world-class connector and cable vendors to drive custom mechanical and electrical designs that meet our unique performance requirements.

Performance Modeling: Conduct trade-off analyses between reach, power, latency, and cost for various interconnect media (Copper vs. Optical).