דרושים » חשמל ואלקטרוניקה » Senior VLSI Design Engineer

We are seeking a highly skilled and motivated VLSI Backend Team Leader to join and lead our dynamic team.
As part of this position, you will lead a team of experienced engineers working on parallel projects, and play a crucial role in the design and implementation of complex designs, flow development, and the latest technology node bring-up and integration.
The Backend team leader will be required to do 50% hands on work and 50% managerial work.

we are looking for a dedicated SoC Clocks Design Automation Engineer to join our Networking Silicon team. In this role, youll focus on developing and supporting clock-related design flows and methodologies for SoC and networking chips, ensuring efficient and high-quality design implementation. Youll also chip in to SoC top-level automation and integration activities, building on existing flow infrastructure to improve efficiency and consistency across projects. Introduction
What you'll be doing:
Develop and maintain design automation and methodologies for SoC and networking clock flows.
Collaborate with design, STA, and project teams to ensure timely and high-quality design closure.
Develop and improve SoC top-level automation scripts and flows built upon existing infrastructure and tools.
Support SoC integration and construction flow activities across multiple projects.
Assist in timing, power, and noise analysis to ensure efficient performance.

In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.

What you'll be doing:

Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.

Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.

Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.

Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.

Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).

Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.

Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.

Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.

Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.

Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

We are looking for a hands-on leader to head a small team that builds simulation models for our next-generation AI hardware and DSP. Modeling is done in several layers, from cycle-accurate, bit-exact block level modeling, to event-driven full IP system flows.
Your groups mission is to take part in the exploration phase of a project, giving architects rapid, high-fidelity feedback so they can explore design options, and to perform algorithmic regression, detecting deadlocks, sweep parameters and features, and understand system-level impact in a quickly adapting, dynamic development environment.
Beyond pure performance modeling, youll keep a sharp eye on functional accuracy and QA, follow emerging academic and industry trends, and inject the relevant insights into the product.
You will also champion modern AI-assisted coding tools (e.g., Cursor AI, GitHub Copilot) to lift the productivity of the senior software engineers on your team and shorten iteration cycles.
Responsibilities:
Lead and mentor a team of simulation and modeling engineers; set goals, review designs, and remove roadblocks. Design and implement transactional / cycle-accurate / bit-exact / event-driven models that faithfully represent advanced AI IP blocks (Transformers, CNN accelerators, custom DMA, interconnects, power-management units, etc.). Build automated flows to sweep architectural parameters and features, collect metrics, and visualize system-level impact on performance, area, power, and bandwidth. Analyze and debug complex issues such as deadlocks, race conditions, and performance hotspots; deliver concise root-cause reports and actionable recommendations. Collaborate daily with architecture, VLSI, compiler, and firmware teams to translate new algorithms and hardware ideas into model requirements and specifications. Own accuracy and QA of the simulation stack: golden-model alignment, coverage tracking, regression health, and release sign-off. Continuously survey academic papers and industry trends, extract meaningful insights, and propose innovative modeling techniques or architectural directions. Promote the adoption of AI-powered development tools to accelerate coding, code-review, documentation, and test generation across the team.

we are looking for a Senior Hardware Architect for Mobile broadband.
As a senior architect you will be a leader, someone who brings into the company new ideas and helps drive next generation wireless products
Responsibilities:
Be a leader in the Mobile Broadband team, architecting state-of-the-art modems for next generation cellular solutions. Investigate, invent, develop, innovate wireless modem components. Drive the implementation phase with the VLSI, Software and Algorithm teams.

we are looking for a R&D Project Manager.
In this role, you will be managing the MBBU projects involving multiple domains including: VLSI architecture, VLSI Design, VLSI verification, VLSI backend, Algorithms and Software. These projects include development of products like cellular modems, Communication Digital Signal Processors and Radar/Lidar baseband with a total of up to 100 R&D engineers involved.
This role is reporting to the MBBU General Manager.
Responsibilities :
Full ownership on all R&D projects of the Mobile Business Unit, including Software, VLSI and Algorithms tasks.
Direct management for the PMO

We are seeking a highly skilled Senior Communication PHY Algorithms Engineer.
This senior role is focused on the end-to-end research, design, and implementation of digital receivers for proprietary drone communication signals.
Responsibilities:
Mathematically characterize complex communication and signal detection problems. Analyze and assess design trade-offs based on both performance metrics and implementation complexity.
Develop and maintain simulations using MATLAB and Python.
Design digital receiver modules to be implemented either by FPGA of SW.
Implement features directly in SW or technically lead and verify the FPGA implementation efforts of the FPGA engineer.
Accompany the integration process of the feature until its end-to-end operation.

Were seeking passionate professionals who thrive in a fast-paced, creative, and collaborative environment - those who want to be part of the next generation of airspace security innovation.
Responsibilities:
Design and implement sophisticated digital signal processing algorithms for applications in areas such as signal processing and wireless communication physical layer.
Collaboration with a multi-disciplinary teams (algorithm engineers, systems engineers, SW engineers, etc.) to design and integrate challenging DSP algorithms for wireless systems.
Enforce high standards for software architecture, ensuring the DSP codebase is scalable, modular, testable, and maintainable.
Conduct thorough performance analysis and optimization of existing DSP systems, identifying opportunities for improvement.
Write clean, efficient, and maintainable code for production systems.
A proactive approach to innovation and a passion for developing high-quality products.

We are seeking an experienced Software Team Leader to lead the design, implementation, and optimization of our graph compiler key backend functionalities. You will own and drive the development of compiler infrastructure that transforms high-level computational graphs into efficient, hardware-optimized execution flows. This role combines deep technical leadership with people management responsibilities.
Responsibilities:
Take full ownership of key components within the graph compiler backend. Lead, mentor, and grow a team of talented software engineers; set priorities, review designs, and ensure timely, high-quality delivery. Drive the definition and the implementation of backend compiler architecture to support various graph IR transformations, optimization passes, and hardware abstractions. Lead the identification and implementation of compiler-level optimizations to maximize performance and efficiency of workloads on target hardware. Drive clear and transparent work planning by balancing performance goals and time-to-market considerations, fostering a proactive can-do mindset across the team. Establish best practices for code quality, testing, documentation, and continuous integration within the compiler team. Work closely with frontend compiler, runtime, architecture and hardware design teams to ensure seamless integration across the software stack.

we are building state-of-the-art accelerated computing platforms that know no boundaries. Our technology is crucial for global innovators, scientists, researchers, and engineersempowering them to transform their boldest concepts into tangible outcomes. Our next-generation Infiniband, NVLink, and Ethernet systems will continue to be at the forefront of connecting and powering the world's most advanced AI clusters.
We seek a highly motivated and experienced Software Architect specializing in Ethernet Switch ASICs to join our team of experts and help shape the future of high-performance ML/AI computing. You will have the opportunity to work on some of the most pioneering technologies and help drive the innovation of our next-generation networks. You will play a key role in defining switching software stacks and Linux kernel networking, and help address new business opportunities in exciting areas. Our Architects also represent our company in open-source projects, technical conferences, and standard development organizations.
What you'll be doing:
Explore networking technologies, features and protocols, hardware/software capabilities, open-source software and drivers for our Ethernet Switch ASICs and Networking platforms.
Be familiar with the Ethernet Switch ASIC hardware and software stacks, as well as with the Ethernet Switch platforms design and characteristics.
Define robust architectures and technical requirements for embedded software, meeting AI/ML workloads' needs and highly performing network operations.
Lead the work with R&D and Validation teams, providing technical guidelines and close support and thorough reviews for detailed designs and test plans.
Collaboration with architects across various fields, including Chip Design, Firmware, Hardware Platforms, and System teams.
Close work with product marketing, program managers, and account managers to ensure the successful execution of projects.
Support engagements with key customers, issue patents, publish white papers and blogs, and be proactive in technical forums and industry working groups.
Promote innovation through the design and implementation of Proof-of-Concept (PoC).