We are seeking a QA Engineer to join our Cloud Testing team. As part of the broader QA organization, youll focus on testing the software layer that enables our products to achieve industry-leading benchmarks in performance and quality. This role involves hands-on testing of cutting-edge cloud and networking features, learning new technologies, and contributing to both manual and automated validation efforts.

What Youll Be Doing:
Design, develop, and execute test plans for new features across software and update releases.
Identify and report bugs, assist in reproducing issues, and collaborate with R&D to isolate root causes and validate fixes.
Perform a variety of tests including functional, regression, performance, and security testing.
Analyze network flows and debug issues through log and system analysis.
Develop automation scripts and contribute to building scalable test infrastructures.

Execute comprehensive testing of AI datacenter networking solutions, focusing on SONiC-based systems, smart NIC integration, and high-performance networking for AI workloads.
Key Responsibilities:
Design large scale testing topologies with GPU/Traffic Generators and execute test cases for SONiC/our company network operating system functionality.
Validate smart NIC performance and integration with SONiC datapath
Perform functional, performance, and stress testing of AI networking scenarios
Develop automated test scripts for regression testing and continuous validation
Execute interoperability testing between different hardware vendors and software versions
Validate RDMA, high-speed Ethernet performance for AI workloads
Test failover scenarios and network resilience under various failure conditions
Document test results, file detailed bug reports, and track issue resolution
Collaborate with development teams to reproduce and isolate defects
Participate in customer proof-of-concept testing and field issue reproduction.

As an SOC Verification Engineer, you will verify the design and implementation of our SOC technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches and NIC SoC product lines. We are working closely with a wide range of aspects - chip design, DFT, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our SOC solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the clock design elements, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our SOC verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

As a Graph Compiler Software Manager, you will lead the development of next-generation graph compiler technology. This compiler is a cornerstone of AI software offering, empowering customers to optimize, map, and execute complex neural networks across architectures with extraordinary efficiency. You will lead a group of talented engineers and team leaders working across domains such as compiler optimizations, graph-level transformations, operator mapping, scheduling, and code generation. We are seeking a visionary and technically strong leader with passion for excellence and impact in one of the most fascinating areas of AI and deep learning.

Key Responsibilities:

Lead the design and implementation of innovative graph compilation flows for AI workloads, from high-level optimizations to hardware-specific backends. Build and guide a strong, innovative, and results-driven compiler team that thrives on solving complex technical challenges. Collaborate with hardware architecture, VLSI, and software framework teams worldwide to ensure seamless integration and maximum performance. Lead the end-to-end delivery of graph compiler components while meeting aggressive KPIs. Establish and execute group planning processes to ensure timely and high-quality delivery. Provide technical and managerial guidance to team leaders and engineers. Define and drive compiler optimization strategies for AI and deep learning workloads.

Our HW team in Israel is looking for a Validation Hardware Test Engineer to join the Hardware Switch Group. The team leads the development of networking infrastructure for our next-generation data centers, focusing on accelerated performance and optimized end-to-end GPU connectivity. We are looking for a hands-on and detail-oriented Practical engineer with strong lab skills, who enjoys working in a dynamic, multidisciplinary environment.

What youll be doing:

Perform board bring-up, validation, and debugging activities in the lab.

Operate lab equipment such as oscilloscopes, power supplies, logic/spectrum analyzers, and multimeters.

Support hardware investigations by reading schematics, analyzing layouts, and completing test procedures.

Document test results and communicate findings clearly to engineering teams.

Work closely with electrical, mechanical, thermal, and system engineers throughout the development cycle.

In this role, as Embedded Software Team Leader, you will lead a software team taking major part in developing AI framework. This framework is at the heart of the AI software offering, with deep impact on multiple hardware and software teams ability to execute state of the art LLM, Generative AI and Neural Networks with extraordinary performance. You will lead a team of creative and result oriented enthusiasts that invent, design, and implement software that enables smooth connectivity between the NPU and Host CPU.

Key Responsibilities:

Lead and manage the Embedded Software engineering team, ensuring high performance and productivity. Oversee the design, development, and implementation. Collaborate with cross-functional teams to integrate solutions. Provide technical guidance and mentorship to team members. Ensure project timelines and deliverables are met. Conduct performance reviews and support professional development of team members. Collaborate globally with architects, HW teams, NPU teams, and other developer teams.

In this role, you will be a key contributor to the design and implementation of AI Graph Compiler software stack for Neural Processing Units (NPUs). You will take part in defining software architecture, implementing performance-critical components, and enabling efficient execution of advanced neural networks under tight power, memory, and latency constraints.

You will work closely with hardware and system architects, software and hardware engineers, influencing both software and hardware decisions. You will design and implement major parts of NPU embedded solutions, actively promoting AI capabilities to the customers.

What will you do:

Own and design key components of the AI Graph Compiler software stack for NPU-based systems.

Optimize inference performance (latency, throughput, memory footprint, power) for edge deployments.

Collaborate on HW-SW co-design, influencing NPU architecture.

Support IP evaluations and silicon bring-up, root-cause complex HW/SW issues, and influence development methodologies.

Mentor junior engineers and contribute to technical best practices.

The AI Graph Compiler Engineer will design and develop next-generation graph compiler technologies enabling efficient execution of advanced AI models on Neural Processing Units (NPUs) used in edge and embedded AI devices. In this role, you will work at the intersection of AI frameworks, graph optimization, and hardware acceleration, enabling efficient execution of neural networks on cutting-edge AI hardware.

You will work at the intersection of AI frameworks, compiler infrastructure, and hardware acceleration, helping translate high-level AI models into highly optimized executions on NPUs.



What will you do:

Develop and enhance AI graph compiler components targeting NPU architectures. Implement graph-level optimizations such as operator fusion, scheduling, memory planning, and layout transformations. Participate in lowering models from AI frameworks (e.g., PyTorch, ONNX, TensorFlow) into NPU-optimized representations. Contribute to compiler passes focused on performance, memory efficiency, and numerical correctness. Collaborate closely with hardware, runtime, and AI framework teams to achieve optimal end-to-end performance. Analyze performance bottlenecks and assist in compiler-based optimizations. Debug and resolve issues across compiler, runtime, and hardware layers. Support testing, validation, and documentation of compiler features.

We are looking for a System Test Engineer to join our System Test team, responsible for defining, developing and performing tests on a system level for our next-gen Wi-Fi products. Our team embraces modern development practices and tools to accelerate learning and delivery.

Lead and mentor a team of software engineers developing Sensing AI SDK. Architect and implement high-performance sensing SW components for AI, vision, Audio and voice optimized for vectorize SIMD execution. Collaborate with compiler and DevOps teams to ensure efficient development and deployment. Drive technical excellence through code reviews, design discussions, and continuous improvement. Own the SDK roadmap, planning, and delivery cycles. Engage with customers to enable successful pre-sale processes, support integration and gather feedback.