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Location: Caesarea
Job Type: Full Time
we are looking for a Electrical Post Silicon Validation HW Engineer.
In this role, you will be part of the Switch ASIC Post-Silicon Electrical Validation (EPSV) team.
* Ensure the ASIC operates according to specifications and reliably over time by performing extensive, high-precision measurements using advanced test equipment and procedures.
* Conduct deep-dive investigations, integrating knowledge across hardware, software, and system domains to identify root causes of observed device behavior.
* Handle all chip validation aspects, including:
* Building validation plans.
* Performing EPSV using advanced test and measurement equipment.
* Writing tests in Python over device SDK.
* Executing tests and analyzing results.
You will gain in-depth knowledge of chip architecture, functionality, and operating modes, enabling you to debug and resolve electrical chip-related issues.
Requirements:
* Bachelors degree in Electrical or Computer Engineering.
* At least 3 years of experience in hardware or post-silicon validation.
* Hands-on experience with lab equipment performing high-speed, clock, and precise voltage measurements.
* Knowledge of high-speed interfaces and high-power DC/DC design.
Preferred Qualifications
* Experience bringing up ASICs on EVBs with Board Design, FPGA, SerDes, and Software teams.
* Proficiency in debugging issues in the lab using VNA/TDR, oscilloscopes, and phase noise analyzers.
* Experience developing testing environments, performing validation activities, and analyzing data.
* Familiarity with production testing and yield improvement.
This position is open to all candidates.
 
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לפני 10 שעות
חברה חסויה
Job Type: Full Time and Hybrid work
We are searching for the best talent for an Senior Hardware Analog Engineer role, to join our team located in Yokneam, Israel.Purpose: The ideal candidate will have a strong background in analog circuit design, PCB layout, and electronic engineering principles.
This role involves designing, developing, and testing analog circuits for EP applications.

You will be responsible for:
Design and develop analog circuits, including amplifiers, filters, and power management systems.
Create and maintain schematic diagrams and PCB layouts using industry-standard software (OrCAD, PSPICE)
Collaborate with cross-functional teams to define design requirements and project specifications.
Conduct simulations and analyses to validate circuit performance and reliability.
Troubleshoot and resolve design issues during testing and production phases.
Provide technical guidance and mentorship to junior engine
Requirements:
Bachelors degree in Electrical Engineering, Electronics, or a related field.
Minimum of 5 years of experience in analog board design.
Proficient in using circuit design and simulation tools (e.g., SPICE, Altium, Cadence).
Strong understanding of analog circuit theory and applications.
Experience with high-performance analog design and PCB layout techniques.
Excellent problem-solving skills and attention to detail.
Ability to work effectively in a collaborative team environment.
Knowledge of digital circuit design and mixed-signal systems.
Familiarity with regulatory standards and compliance for electronic products.
Experience with prototype development and testing methodologies.
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
Requirements:
B.Sc/M.Sc in Electrical Engineering or Computer Science from a top university.
5+ or more years of relevant experience required
System Orientation: Strong multi-disciplinary approach with multitasking capabilities.
Major Advantage: Specialization in Communication and Signal Processing.
Experience: Hands-on experience with lab work is advantageous.
Technical Skills: Proficiency in C++, Python, and Matlab is a plus.
This position is open to all candidates.
 
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Location: Caesarea
Job Type: Full Time
We are looking for a talented and experienced engineer to take part in the verification efforts for the companys core product. This position involves building and maintaining a complex verification environment, and defining and executing a test plan. In this role, you will be leading all aspects of verification and will have a critical impact on the company's R&D path.
Responsibilities
Define and implement robust SV/UVM verification solutions, including test benches and methodologies, to drive efficient verification closure across block-level and full-chip designs, integrating Mix-signals SoC simulation environment using Verilog, MATLAB, HW/SW Co-simulation and lab integration.
Work closely with Digital Design, Analog Design, Software, Back-end, SW and System teams to understand the functional, power and performance goals of the product and ensure its quality.
Requirements:
Electrical Engineering B.Sc., Computer Engineering or other relevant engineering department graduate with high scores, or equivalent experience.
5+ years in design verification, with strong SV/UVM proficiency (Less experienced engineers with high university grades or vast knowledge in RTL design will also be considered)
Self-motivated, ability to work, lead and drive tasks to completion.
Great interpersonal skills.
Understanding of digital ASIC design flows and SoC development methodologies. experience with SoC/full-chip verification, simulation/debug tools, and Unix/Linux environments, scripting languages (Python, etc.) and version control.
Advantages
Knowledge in Low Power technics and UPF standard.
Knowledge with Mix signals SoCs.
Knowledge with SW/HW Co-development.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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Location: Tel Aviv-Yafo and Caesarea
Job Type: Full Time and Hybrid work
we are looking for a ASIC Logic Design Engineering Technical Leader.
our Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
​Minimum of 8 years of proven experience in a relevant field
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
Join the PHY system team, a pivotal part of silicon development. Our team focuses on the PHY and system aspects of our devices, including PHY firmware, calibrations, system definitions, operations, and post-silicon validation.
Key responsibilities include:
Working with the latest silicon technologies and processes to build large-scale, complex devices at the forefront of feasibility.
Contributing to the development of PHY firmware and system calibrations.
Participating in system definitions, operations, and post-silicon validation activities.
Requirements:
Education: B.Sc/M.Sc in Electrical Engineering or Computer Science from a top university.
3+ years of relevant experience required
System Orientation: Strong multi-disciplinary approach with multitasking capabilities.
Major Advantage: Specialization in Communication and Signal Processing.
Experience: Hands-on experience with lab work is advantageous.
Technical Skills: Proficiency in C++, Python, and Matlab is a plus.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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חברה חסויה
Location: Caesarea
Job Type: Full Time and Hybrid work
we are looking for a Senior Asic Design.
Your Impact:
Write and review micro-architecture specifications
Implement RTL (Verilog/SystemVerilog) to meet timing, performance, and power requirements
Contribute to full chip integration, timing methodology, and analysis
Collaborate with verification engineers to resolve bugs and achieve coverage closure
Work with the physical design team to close timing and PnR issues
Support design methodology evolution and best practices
Perform debug, root-cause analysis, and post-silicon validation in the lab
Requirements:
B.Sc./M.Sc. in Electrical Engineering from a top university
RTL design experience
Familiarity with UVM and functional verification methodologies
Preferred Qualifications:
Experience with MATLAB simulations and bit-exact modeling environments
Familiarity with mixed-signal systems and environments
Knowledge and hands-on experience with Clock Domain Crossing (CDC)
This position is open to all candidates.
 
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חברה חסויה
Location: Caesarea
Job Type: Full Time
Required Logic Design Engineer
Responsibilities
Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities.
Requirements:
Bachelor's Or Master's degree in Electrical Engineering, Computer Engineering, or a related field
Minimum 5 years of experience in logic design, working in both IP and SOC environments
Proficiency in Verilog or SystemVerilog for design
Experience with industry-standard EDA tools (Synopsys VC, Cadence etc)
Knowledge in low power design techniques
Knowledge of RTL synthesis and timing analysis flows
Strong communication and teamwork abilities
Excellent problem-solving and debugging skills
Advantage
Experience with Analog ICs, Mix-signals design, and Lab equipment
Experience with RISC-V based SoC and FW.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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2 ימים
חברה חסויה
Location: Caesarea
Job Type: Full Time
We are looking for a highly motivated and experienced Senior Verification Engineer to perform and guide design verification for the electro-mechanical portions of the system design.
For this role, were focusing on electrical and mechanical parts, assembly and functional aspects of the system design. This is an ideal opportunity for someone who is motivated and passionate to make an impact in leading the development of the next generation of ophthalmic robotic surgery.
Responsibilities
Create verification protocols based on electromechanical design input requirements.
Identify applicable standards for each electromechanical aspect and define how they are addressed in verification activities.
Establish statistical sample sizes according to the risk level associated with each part, assembly, and feature.
Lead protocol development and test execution for sterilization validation.
Guide a team of verification engineers and testers in creating test protocols, executing tests, reviewing results, and generating reports.
Participate as a team member in the development of new features related to electromechanical assemblies and associated robotic capabilities.
Requirements:
BSc degree in Electrical or Mechanical, or Biomedical Engineering.
5+ years of experience in design verification of electrical, mechanical, and multi-disciplinary medical device systems.
Experience with optical systems (e.g., imaging, illumination, lenses, cameras) in medical devices - an advantage.
Proven experience in establishing and justifying statistical sample sizes for verification activities.
Experience with sterilization processes and validation - an advantage.
Familiarity with medical device standards and regulations, such as ISO 13485 and IEC 60601.
Excellent verbal and written communication skills in English.
Strong problem-solving abilities, attention to detail, and the ability to quickly learn new technologies and systems.
This position is open to all candidates.
 
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1 ימים
חברה חסויה
Location: Caesarea
Job Type: Full Time
looking for a highly motivated Field Application Engineer who will work collaboratively with the team as well as independently and develop test applications solutions for our customers.



Responsibilities

Develop, debug, and deploy test solutions for semiconductor devices on Teradyne ATE test systems (HW and SW).
Supporting test program correlations and release to production activities.
Actively engage with customers to develop new test techniques.
Troubleshooting of test issues and improving test methodologies.
Develop customer relations at a technical level.
Collect customer needs and requests, communicate to internal engineering team to develop new solutions for customer.
Work within the support of our worldwide application teams to coordinate project development and on time delivery of critical project milestones.
Requirements:
Bachelors or Masters degree in electrical engineering.
2+ years of experience in semiconductor production testing and debugging.
Programming knowledge (VBA, VB.NET, C, .NET C# or similar).
Excellent execution quality standards.
High self-learning skills.
VBA experience is a big plus.
Knowledge in DFT & test methodologies is a big plus.
Excellent communication skills.
Travel both domestic and international as needed
Strong team player and goal oriented
Able to handle dynamic work environment with pressure and quick changes.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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18/01/2026
Location: Petah Tikva and Caesarea
Job Type: Full Time
We are hiring a Principal Algorithms Solution Architect to lead innovation in algorithm design and system architecture, delivering transformative solutions in graphics, vision, and AI for our next-generation iTero scanners.
The role is located in Petah Tikva or Caesarea
Key Responsibilities:
Lead and execute cutting-edge algorithmic challenges, driving knowledge and breakthroughs across the company.
Play a pivotal role in shaping our algorithmic strategy and influencing performance outcomes.
Provide guidance, mentorship, and leadership to teams, ensuring successful delivery across multiple projects.
Apply advanced troubleshooting skills and collaborate with R&D and Product teams to resolve complex technical issues and ensure system reliability.
Partner with stakeholders to anticipate future challenges and design innovative solutions.
Participate in all phases of the algorithm development cycle, from concept through deployment.
Identify risks in algorithm and system design and propose effective solutions.
Evaluate existing solutions and recommend improvements to enhance efficiency, scalability, and robustness.
Consistently demonstrate innovative thinking, systemic understanding, and strong cross-team collaboration.
Maintain a strong leadership presence, fostering accountability, growth, and high performance across the organization.
Requirements:
Ph.D. or equivalent degree in Computer Science, Electrical Engineering, or a related field.
Extensive experience designing and implementing cutting‑edge algorithms in computer graphics, vision, and AI, coupled with proven leadership in guiding teams and driving innovation.
Solid programming skills in C/C++/Python or similar languages.
Exceptional interpersonal and communication skills.
Proven leadership abilities, with experience guiding teams and fostering collaboration.
High-level systemic understanding and the ability to troubleshoot and resolve complex challenges.
This position is open to all candidates.
 
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