דרושים » הנדסה » Physical Design Engineer

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will:
Establish and lead a Back-End team with emphasis on RTL to GDS flow, Floorplan, Synthesis, Place and route, clock-tree, STA, layout, signoff (Timing, DRC, LVS) and Power
Be responsible for the Backend execution and methodologies
Be responsible to guide and lead contractors

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role, you will be:
Responsible for definition and micro-architecture of complicated digital blocks
Detailed documentation and RTL implementation including running EDA tools (Lint, CDC, simulation, debugging, synthesis and timing analysis)
Work closely with verification and architecture team
Participate in design methodology and tool automation work as needed

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
About The Position:
DFT (Design For Test) is a multidisciplinary field which involves many aspects of the chip design process, including: DFT architecture definition, RTL design, verification, backend implementation, STA, pre and post production activities and many more.
You will be part of a growing team that develops from scratch its DFT implementation flow and responsible for all DFT activities and you will closely work with multiple teams within the VLSI group.

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems. If youre driven by solving problems, some dont yet have names, this is where you want to be.
In this role you will:
Develop and maintain all aspects of the emulation environment- Emulation model, Test plan, Validation environment
The Emulation engineer is involved in validation of significant aspects of ASIC development-chip performance, SW-HW API , system boot and functional flows
Expect to work closely and be part of the development process of the RTL design, verification, software development, testing, and more
Participate in design methodology and tool automation work as needed

Were building the next Gen. AI Factory, at a leading AI Infrastructure technology company. Our products sit at the core of rack-scale computing and define the performance and scale of AI systems.
If youre driven by solving problems, some dont yet have names, this is where you want to be.
The role Includes:
Develop ASIC verification environment for full chip, sub-cluster and unit levels. Responsibility for generation and execution of verification plan for challenging digital blocks/chip Development of System Verilog, UVM based protocol/traffic generators, monitors, checkers and coverage, Learn and work with great teammates

The EyeQ SoC Performance Modeling and Profiling team is part of the EyeQ Platform Group (EPG), working on both current and next-generation designs for ADAS (Advanced Driver-Assistance Systems) and Autonomous Vehicles (AV). Performance models and profiling tools are essential components of the EPG infrastructure they are used during the hardware architecture definition phase of the EyeQ chip and by software developers to optimize performance.
What will your job look like:
You will be part of team that develops EyeQ SoC Performance Modeling environment and emulators
You will work on SOC performance analysis and optimizations.
You will be running HW benchmarks, to measure HW performance and to calibrate the simulation environment to match the performance of the silicon board.
You will be working on HW performance analysis and tuning, and influence future company EyeQ SoC design.
You will have the opportunity to work on open-source simulation and profiling tools and adopt them to our company's needs.
You will work closely with HW architects and SW/Algorithms developers.

seeking a System Software Validation Lead to define validation methodologies, set quality standards, and drive a culture of quality across multidisciplinary hardware and software systems. This leadership role emphasizes process ownership, methodology enforcement, and coaching teams, while also providing technical guidance and hands-on validation expertise.