דרושים » חשמל ואלקטרוניקה » DFT ATPG Engineer

We are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.

As a design engineer in the DFT design team, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.

What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
As a System on a Chip (SoC) Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers , our company Cloud customers, and billions of our company users worldwide.

We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
Insert MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

We are looking for a DFT Verification Engineer for developing the next generation DFT technologies.

As a DFT Verification Engineer, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.

What you'll be doing:

In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.

As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.

Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.

We are now looking for a Senior Security Validation Architect for Networking AI Platforms! NVIDIA is seeking an outstanding security architect with deep expertise in security validation and advanced testing methodologies to help design, build, and guide secure validation across our next-generation products. The candidate is expected to deliver highly innovative validation and verification solutions that lead to significant industry differentiation and help achieve the long-range goals of the Security organization. Leaders in this role will strengthen NVIDIAs Data Center and networking products against emerging threats while driving adoption of future-proof security validation technologies.

What youll be doing:

Defining and driving implementation and adoption of security validation strategies across NVIDIAs networking platforms security solutionsspanning Silicon, Firmware, and System levels.

Designing frameworks and automation flows to test and verify security functionality during product QA, large-scale manufacturing, and in-field operation.

Collaborating with architecture, design, and product engineering teams to ensure robust verification coverage for hardware roots of trust, secure boot, key provisioning, and cryptographic services.

Driving development of advanced validation and debugging tools capable of detecting complex security anomalies, misconfigurations, and behavioral deviations across systems.

Building and maintaining an end-to-end visibility architecture for security validation metrics, enabling continuous trust across the product lifecycle.

We are looking for a Formal Verification Engineer for our Networking team!

This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. We have the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.

What you'll be doing:

In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.

You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our core technology.

Learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.

We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.

We are looking for a creative and independent Test Engineer for Reliability . Our Networking unit has continuously reinvented itself over two decades. Our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions We're looking to grow our company and build our teams with people who can join us at the forefront of technological advancement. We need a creative individual who will help transfer Network Silicon ICs products (Switch, NIC, SmartNic) from design engineering to mass production.

You will be exposed to various aspects of design, DFT and test of our network IC products, and will be responsible for definition and development of tests for reliability stressing of Network-ICs. In addition, your responsibilities will include working with production test and HW teams. If you are passionate about enabling of the highest quality Network products that will change the world, we want to hear from you!

What you'll be doing:

Developing test patterns and test programs for reliability evaluation.

Investigation and debug of test patterns covering a wide range of IPs and different test methods , including HW issues .

Implement IC accelerated stress tests on tester and HTOL platforms.

Developing and improving work procedures and methodologies. Working together with multiple groups silicon design, system and product engineering, test engineering, hardware and operations.

Working with analog and digital design teams, DFT, as well as Backend team for reliability stress and test definitions and problem solving.

Development and integration of system level testing for accelerated life-test.

We are looking for a best-in-class Chip Design HW Emulation Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a significant part in emulating our groundbreaking and innovative chips, enjoy working in a meaningful, growing, and highly professional environment where you make a huge impact in a technology-focused company. Join our world-class emulation team in Israel. Our focused team takes Switches/NICs/SoCs designs and program the emulators to behave like our silicon. Are you ready to take on interesting problems and craft solutions? Come check out our team.

What you will be doing:

Responsible for emulation and prototyping of complex chip designs.

Define methodologies and develop infrastructure to enable fast integration of large chips into hardware emulation platforms.

Collaborate closely with design, verification, and software teams to support embedded and application software development.

Connect emulator/FPGA-based solutions to real external hardware or virtual targets.

Manage complex testbenches and support various hardware/software protocols.

Perform RTL design, verification, FPGA partitioning and implementation.

Develop scripts to automate flows and improve efficiency.

Bring up and debug designs in the lab environment.

Work in a cross-functional, hands-on engineering role that spans hardware and software domains.

Our Networking System Product Engineering team is looking for an excellent Test Design and Validation Engineer. The position requires an understanding of HW and SW to provide stable, efficient, smoothly running production tests, to enable high availability, while ensuring the quality of the products being shipped to customers. The position combines design and hands-on infrastructure development, implementing and maintenance of sophisticated tools that improves development workflow and overall productivity.

What youll be doing:

Design and develop automated tests for networking Switches and Adapters while working closely with the HW, ASIC, and SW Engineering teams to achieve a reliable test with high coverage.

Exposed to various aspects of design, DFT, and test of our next-generation network products.

Take a significant part in the definition and development of tests from the development level to the final test of Network-Systems.

Utilize test suites to find, debug and resolve problems with production process.

Ability to drive projects to full execution in time and working under pressure of schedule and multi project environment.

Supporting and fix bugs of existing code. Supporting production lines for: deployments, patches, maintenance.

Test Verification and Validation (both HW and SW). Troubleshooting and streamlining/optimizing our testing procedures.

Execute tests in different scopes such: regression, performance degradation, functional, and security; report the progress of testing and provide summary reports of the activity.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will use your ASIC design experience to be part of a team that develops the ASIC SoC from Plan of Record (POR) to Production. You will be creating SoC Level micro architecture definitions, RTL coding and will do all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies. You will collaborate with members of architecture, software, verification, power, timing, synthesis dft etc. You will face technical tests and develop/define design options for performance, power and area.
The AI and Infrastructure team is redefining whats possible. We empower our company customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers, our company Cloud customers, and billions of our company users worldwide.
We're the driving force behind our company's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for our company Cloud, our company Global Networking, Data Center operations, systems research, and much more.
Responsibilities
Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.
Participate in architecture feedback.