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לפני 3 שעות
Location: Yokne`am
Job Type: Full Time
We are looking for a Physical Design Engineer.
Roles and Responsibilities:
Build, maintain, and optimize CAD tools infrastructure supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate IC layout flows, including placement, routing, floorplanning, PCells, and tapeout preparation.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Design and implement testing frameworks, regression suites, code review practices and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.
Requirements:
B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering (hands-on IC layout/CAD experience also considered).
13 years of relevant industry experience or 3+ years for more senior candidates both junior and experienced engineers will be considered.
Hands on experience with layout and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, TCL, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and layout workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, with the ability to work independently in a dynamic, fast-paced environment.
Preferred:
Prior experience as a Layout Engineer or EDA/CAD Physical Design Engineer in a semiconductor environment.
Deep understanding of IC physical design and verification flows:
Custom analog/digital layout, floorplanning, placement, routing
DRC, LVS, ERC, parasitic extraction
Physical verification and tapeout readiness
Advanced SKILL programming for layout automation and productivity.
Experience with tapeout preparation, design rule integration, and physical verification.
Knowledge of PCells, parameterized devices, and layout generators.
Proficiency in physical verification runset programming and maintenance, including customization of DRC/LVS/ERC decks and integration into design flows.
Experience building automated regression environments for CAD/EDA flows in SKILL.
Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.
This position is open to all candidates.
 
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לפני 4 שעות
חברה חסויה
Location: Yokne`am
Job Type: Full Time
Join a dynamic and innovative team driving the development of state-of-the-art EDA/CAD tools and scalable design automation infrastructure to empower advanced integrated circuit (IC) design. You will design, develop, and maintain next-generation design robust software tools and workflows across all domains in integrated circuit design, while ensuring compatibility with legacy software solutions.
Roles and responsibilities:
Build, maintain, and optimize CAD tools supporting both commercial and in-house layout and verification tools (Cadence Virtuoso, Synopsys ICC, Mentor Calibre, etc.).
Develop and automate design flows spanning frontend RTL-to-GDSII, digital backend implementation, and physical/verification signoff, ensuring scalability and tapeout readiness.
Collaborate with layout, circuit, and verification teams to capture requirements and deploy efficient automation workflows.
Apply advanced software engineering and CAD methodologies to address technical challenges, evaluate architectural and hardware constraints, and deliver scalable automation solutions.
Design and implement testing frameworks, regression suites, code review practices, and CI/CD pipelines to validate CAD flows, ensure correctness, and improve reliability.
Define, document, and enforce best practices, standards, and procedures; provide technical guidance, training, and support to engineering teams.
Requirements:
B.Sc. in Electrical/Computer Engineering, Computer Science, or Practical Engineering, or equivalent hands-on IC CAD/EDA experience.
Hands-on experience with physical design and verification tools, including both commercial (Cadence, Synopsys, Mentor) and in-house CAD solutions.
Strong programming skills in SKILL, Python, Tcl, Perl, and Shell (Csh, Bash).
Ability to debug, optimize, and troubleshoot CAD flows and physical design workflows.
Familiarity with regression testing, code review, flow validation, and CI/CD practices in CAD/EDA environments.
Strong communication and teamwork skills, and the ability to work independently in a dynamic, fast-paced environment.
Preferred:
Prior experience as a CAD/EDA Engineer or Physical Design Engineer in a semiconductor environment.
Deep understanding of IC physical design and verification flows:
Floorplanning, placement, routing, power, and clock distribution
DRC, LVS, ERC, parasitic extraction
Physical verification and tapeout readiness
Advanced SKILL programming for automation and productivity.
Experience with tapeout preparation, design rule integration, and physical verification.
Knowledge of PCells, parameterized devices, and flow generators.
Proficiency in physical verification, runset programming, and maintenance.
Experience building automated regression environments for CAD/EDA flows.
Experience with in-house CAD tool development and with the integration and customization of both in-house and commercial solutions.
This position is open to all candidates.
 
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לפני 4 שעות
חברה חסויה
Location: Yokne`am
Job Type: Full Time
We are looking for talented and ambitious individuals to join our Yoqneam IC team.
Roles and responsibilites:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.
Preferred:
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.
This position is open to all candidates.
 
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6 ימים
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be in charge of developing physical design, synthesis, STA and Logic eq methodologies for implementation of networking chips and SOCs.

Work closely with block owners. full Chip STA engineers and project managers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for chip floorplan, power and clock distribution, P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

At least 2 years of relevant experience

Proficiency using Python, Perl, Tcl, Make scripting.

Expertise in analysing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep-sub micron processes.

Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power required and implementing them through ECOs is required.

Knowledge in process variation effect modelling and experience in design convergence taking into account variations.

Successful track record of delivering designs to production is necessary.

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Ways to stand out from the crowd:

Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/Tempus)

Experience in methodology definition / flow owner of synthesis / Place and Route/ STA steps is an advantage.

Great teammate.

Ownership, self-learning skills, and ability to work autonomously.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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3 ימים
Location: Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon Engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Physical design of blocks according to specifications under challenging constraints targeting for the best power, area, and performance.

Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.

Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.

Taking part in flows development.
Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering or equivalent work experience.

5+ years of experience in Physical Design.

Proven experience in RTL2GDS flows and methodologies.

Knowledge in physical design flows and methodologies (PNR, STA, physical verification).

Deep understanding of all aspects of Physical construction and Integration.

Strong background of Physical Design Verification methodology LVS/DRC.

Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc).

Great teammate.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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תודה על שיתוף הפעולה
מודים לך שלקחת חלק בשיפור התוכן שלנו :)
6 ימים
Location: Yokne`am
Job Type: Full Time
We are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.

Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.

Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.

Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.
Requirements:
What we need to see:

B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).

2+ years of fulltime relevant experience in the areas listed below.

Proven experience and strong knowledge in key technical domains, including: Physical Design, Backend CAD (Computer-Aided Design), STA (Static Timing Analysis) and Timing closure methodologies.

Familiarity with industry-standard tools like PrimeTime (STA) and PrimePower (Power Estimation).

Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.

Strong sense of ownership, self-learning skills, and ability to work both independently and collaboratively with internal and global teams.

Ways to stand out from the crowd:

Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality).

Knowledge in Tcl/Perl/Python.

Versatile.

Great teammate.
This position is open to all candidates.
 
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30/10/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
Our networking VLSI team is looking for a CAD engineering manager. The team is providing methodologies and vendor-based EDA flows for the physical design execution teams. Your team will be responsible for defining and developing methodologies and flows that enable high quality and super-efficient execution of over a hundred physical design engineers. You will be working closely with the physical design technology team, with design engineering professionals and project leads, and with peer software/CAD teams, hence you will need to possess strong interpersonal skills, be a quick learner, and manage multiple missions in a results-oriented manner. You, along with the team, will lead processes from requirements understanding, through software definition and implementation of tools/flows, ending with release, integration and support.

What you'll be doing:

Lead a growing team of ~5 professional CAD engineers.

Own the definition, development, and maintenance of software solutions for physical design engineering.

Collaborate and closely interact with design technology experts and execution engineers, along with software/CAD peers.

Influence and make right choices to produce high quality and tangible impact.

Be agile and make continuous and incremental progress by decomposing the problem in to smaller and achievable goals.

Define and build strategic vision for the networking VLSI technology and EDA team.
Requirements:
B.Sc. in Computer Science or Electrical Engineering.

8+ overall years of EDA/CAD/software development experience.

2+ years of team management experience.

Experience with vendor tools (Synopsys, Cadence etc).

Proficient at scripting: Perl, Tcl, Python, shell etc.

Familiar with revision control systems.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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13/10/2025
חברה חסויה
Location: Yokne`am
Job Type: Full Time
We are seeking a CAD Engineer to join our team. In this role, youll contribute to the development and automation of flows, tools, and methodologies (TFM) in the backend power domain as well as at the architecture and micro-architecture levels. This is a cross-functional role that blends software engineering excellence with deep insight into chip development processes.

Success in this role requires strong communication skills, a creative and data-driven mindset, and a passion for delivering high-quality results.

What youll be doing:

Develop and support tools flows and methodologies in backend power design of networking chips and SOCs .

Collaborate with backend engineers, architects and micro architects to support and improve design process.

Be responsible for the full lifecycle of tool development from design (data storage and UI) to testing, deployment, and maintenance.
Requirements:
What we need to see:

B.Sc. or higher in Computer Science, Electrical Engineering, or a related field.

2+ years of relevant experience.

Strong interpersonal skills collaborative, proactive, and eager to learn.

Solid programming skills in multiple languages.

Ways to stand out from the crowd :

Familiarity with EDA power estimation tools such as PrimePower.

Understanding of power consumption concepts in VLSI and familiarity with methods for estimation and optimization.

Proficiency in scripting languages like Tcl, Python, Perl, or Shell scripting.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 3 שעות
Location: Yokne`am
Job Type: Full Time
We are looking for Emulation & Prototyping Engineer.
Roles and responsibilities:
Build and maintain FPGA/emulation platforms for large-scale SoC/ASIC designs.
Map RTL designs to FPGA/emulation platforms.
Develop test environments and infrastructure for HW/SW co-verification.
Support hardware bring-up and software validation on emulation platforms.
Collaborate with verification engineers to run regressions and accelerate debug cycles.
Optimize partitioning, synthesis, and runtime performance on emulation systems.
Work cross-functionally with RTL design, verification, and firmware/software teams.

Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
47 years of experience in FPGA prototyping or emulation of ASIC/SoC designs
Strong understanding of digital design and RTL (Verilog/SystemVerilog/VHDL).
Hands-on experience with at least one emulation/prototyping platform (Palladium, Protium, Veloce, ZeBu, or FPGA-based)
Good knowledge of synthesis, timing closure, and design partitioning for FPGA/emulation.
Familiarity with verification methodologies and environments (UVM/SystemVerilog/C).
Experience with scripting (TCL, Python, Perl, or Shell) for automation.
Strong problem-solving and debugging skills.
Ability to work in a fast-paced, collaborative environment.
Excellent communication and teamwork skills.
Preferred:
Exposure to software bring-up, driver validation, or firmware testing on emulation.
Knowledge of bus protocols (Ethernet, DDR, etc.).
Experience with debug tools (waveform viewers, logic analyzers, or emulation debug frameworks).
Background in SoC architecture and hardware/software co-design.
This position is open to all candidates.
 
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13/10/2025
Location: Yokne`am
Job Type: Full Time
We are looking for a skilled and experienced Engineer with a focus on System Electrical Validation to join our Engineering team in Yokneam, Israel. As part of this role, you will play a crucial role in ensuring the quality of our advanced products. You will collaborate closely with PHY design, system architecture and company wide system, validation, reliability, signal integrity and testing owners to devise and implement effective validation strategies, aligning with our high-quality standards.

What youll be doing:

Create and implement electrical validation plans for new products.

Analyze and interpret validation results to identify potential issues.

Collaborate with design and architecture teams to define required validation and optimize and solve electrical issues.

Design and develop test scripts and frameworks to automate validation processes.

Work closely with software and firmware teams to ensure seamless integration.

Provide technical expertise and guidance to junior team members.

Maintain accurate documentation of validation activities and results.
Requirements:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.

5+ years of proven experience in electrical validation.

Ability to analyze analog circuits and analog issues.

Familiarity with I/O protocol and electrical compliance and validation.

Proficiency in scripting languages such as Python, Perl, or Shell.

Excellent problem-solving and analytical skills.

Ability to work collaboratively in a fast-paced and dynamic environment.

Exceptional communication and interpersonal skills.

Fluency in English.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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30/10/2025
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are on the lookout for a dedicated and driven Software Engineer to join our dynamic VLSI Design Automation team. This team focuses on the development of VLSI CAD tools and web applications, and is responsible for managing and maintaining high-quality VLSI infrastructure, including compute and storage for the Backend Networking team. We seek a passionate engineer eager to effectively manage compute and storage, develop scripts, automate processes, and create dashboards and applications. Our ideal candidate is someone with experience in VLSI methodologies, data-driven, eager to learn, and possesses strong interpersonal skills.

What youll be doing:

Oversee and optimize compute and storage resources, ensuring operational efficiency and success of VLSI projects. Develop and maintain scripts and automation tools to streamline infrastructure tasks.

Engaging in the entire lifecycle of tool and web application development, which includes backend, frontend, data storage design, UI/UX design, testing, deployment, and maintenance.

Design, implement, and maintain dashboards for monitoring and reporting on infrastructure performance and usage.

Challenge existing VLSI methodologies to have better tools and flows.
Requirements:
What we need to see:

A bachelors degree in computer science/engineering, electrical engineering, or equivalent experience.

3+ years of experience in VLSI Design Automation.

Strong knowledge of Python.

Experience with data visualization in Python.

Knowledge in LSF job scheduler.

Proficiency with the Linux operating system.

Ways to stand out from the crowd:

Knowledge in VLSI flows.

Familiarity with database management systems, both SQL (e.g., PostgreSQL, MySQL) and NoSQL.

Experience with data analysis tools and libraries (e.g., pandas, NumPy) is a plus.

Prior experience with machine learning techniques and frameworks.

Familiarity with CI/CD practices and tools.
This position is open to all candidates.
 
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