דרושים » תוכנה » Senior ASIC Frontend Design Engineer

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Roles and responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level ASIC, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Lead the end-to-end execution, tracking, and convergence of chip-level CDC and RDC for complex SoCs across all IPs and partitions.
Plan and orchestrate CDC/RDC signoff: define methodology, scopes, run plans, constraints, and acceptance criteria.
Run and maintain CDC/RDC flows and rule decks, including multi-mode, multi-clock, and hierarchical signoff.
Triage violations efficiently: root-cause to RTL, constraints, tool setup, or IP models; prioritize and drive fixes to closure with owners.
Verify reset architecture and RDC robustness (reset domain intent, release sequencing, glitch detection, fanout).
Author and review CDC/RDC constraints, waivers, and justifications; ensure auditability and signoff quality.
Automate runs, report parsing, dashboards, and KPIs for closure tracking using scripting and data tooling.
Partner with RTL, DV, DFT, STA, PD, and Architecture to align fixes, manage ECOs, and protect CDC/RDC quality during late design changes.
Define and enforce signoff gates; communicate progress and risks with clear metrics and issue tracking.
Continually improve methodology and training to prevent recurring CDC/RDC issues and accelerate convergence.

we are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.
As a design engineer in the DFT design team at our company, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

we are at the forefront of AI-driven innovation in VLSI design automation. Join us to shape the future of semiconductor design with cutting-edge AI tools and make a significant impact in a collaborative, high-performance environment. Are you ready to push the boundaries of whats possible in VLSI CAD? Come be part of our pioneering team!
What you'll be doing:
You will be responsible for developing and integrating advanced CAD solutions and automation flows using AI and machine learning for VLSI design, verification, and implementation.
Work closely with design, verification, and CAD teams to identify areas for improving VLSI workflows using advanced tools and methods.
Research, prototype, and deploy AI-based algorithms.
Develop and maintain scripts and automation infrastructure to enable seamless adoption of AI tools in the VLSI design process.
Continuously review emerging AI technologies and methodologies to keep our CAD environment up-to-date.
Provide technical support and training to engineering teams on AI-enabled CAD flows and best practices.

We are now looking for a Power Optimization and Analysis Engineer! our company prides ourselves on having energy-efficient products. We believe that continuing to maintain our products' energy-efficiency compared to competition is key to our continued success. As part of the u/arch team in the Switch group, you will be responsible for analyzing full chip and unit-level power data and driving the FE/BE ASIC teams to improve their units power efficiency; you will be responsible for researching, developing, and deploying methodologies to help our company's products become more energy efficient. Key responsibilities include developing techniques to model, analyze, and reduce power consumption of our company Switches product line.
As a member of Switch u/arch Team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study and implement power analysis and reduction techniques for our company's next generation switches. Your contributions will help us gain early insight into energy consumption of graphics and artificial intelligence workloads, and will allow us to influence architectural, design, and power management improvements.
What You'll Be Doing:
Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
Develop and share best practices for performing pre-silicon power analysis.
Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
Select and run a wide variety of workloads for power analysis.
Prototype new architectural features in Verilog and power analysis.

We are looking for a creative and independent Product Engineer with production testing experience - test development/integration, test hardware, Burn-In, HTOL and similar. our company Networking unit has continuously reinvented itself over two decades. Our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another. Today, we are increasingly known as the place for getting End-to-End High-Speed Ethernet and InfiniBand Solutions We're looking to grow our company and build our teams with people who can join us at the forefront of technological advancement. We need a talented individual who will help transfer Network Silicon ICs products (Switch, NIC, SmartNic) from design engineering to mass production with top quality products.
You will be part of the IC product development group, exposed to various aspects of DFT and test of our company network IC products, and will be responsible for integrating the definition and development of Burn-In platform, HW and tests for reliability stressing of Network-ICs. In addition, your responsibilities will include working with production sites, test a nd HW teams, design and operations. If you are passionate about enabling of the highest quality Network products that will change the world, we want to hear from you!
What you'll be doing:
Plan, drive and execute the implementation of IC accelerated stress testing for Integrated Circuit devices to assure high reliability throughout life cycle.
Develop and optimize work procedures and methodologies. Working together with multiple groups system and product engineering, test engineering, hardware and operations.
Drive transition of HTOL HW into Production BI environment working with HW teams.
Drive releases of test programs for Production Burn In optimizing stress types and stress time
Investigation and debug of test patterns including HW issues as necessary.
Working with local and global Reliability, Test, DFT, stress and test on definitions, implementation and problem solving
Lead IC reliability activities on various product lines and cutting-edge technologies .

we are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at our company Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.

our company Networking IC Product Engineering team is looking for a Post Si Circuit marginality Validation engineer, to take part of Network ASIC & SOC validation and characterization efforts of speed, logic, memory, analog circuits and power features. You will be part of a team working on groundbreaking technology. We are in need of hardworking and motivated engineers ready to define and lead validation activities. If you have a passion for lab work, data analysis, and post-Si hands-on problem-solving, we will be happy to have you on our team!
We are looking for a skilled and experienced Engineer with a focus on Post Silicon IC and PDN Validation to join our Engineering team in Yokneam, Israel. As part of this role, you will play a crucial role in ensuring the efficient power, performance and quality of our advanced products. You will collaborate closely with chip design, architecture, and company-wide power owners to devise and implement effective validation strategies, aligning with our high-quality standards.
What youll be doing:
Build and implement power delivery and transients validation plans for new products
Analyze and interpret validation results to identify potential issues and define required margins.
Collaborate with design and architecture teams to determine efficient power and performance targets.
Craft and develop test scripts and frameworks to automate validation processes.
Work closely with software and firmware teams to ensure seamless integration.
Conduct system-level testing to ensure the successful implementation of power and performance features, validate transient behaviour and debug complex problems.
Provide technical expertise and mentorship to junior team members.
Maintain accurate documentation of validation activities and results.

Are you passionate about working on a team that is at the cutting and bleeding edge of hardware technology? Our Design-for-Test Engineering team at our company works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most sophisticated semiconductor chips. We are looking for an experienced DFT Engineer to join the ATPG team. The position includes taking part in development of the next generation DFT technologies and working closely with a wide range of our groups and aspects - chip design, backend, verification, and production testing.
Working on the most advanced technologies and complex products, our DFT solution are unique and innovative internal developments, and we are continuously improving and evolving the solution to meet the challenging goals. If you find groundbreaking Technologies, and next generation products interesting, then this is the team for you. Take opportunity to join our team for an exciting and educational environment, where every individual has significant contribution to our products and achievements!
What youll be doing:
You will be in charge of state of the art Design for Test/ATPG flows and implementation
Take full ATPG ownership end to end on a project, from Arch & planning to pattern generation, verification and post Silicon bring up and diagnosis.
Inventing and maintaining automation flows that provide the short test time to production.

We are now looking for a Formal Verification Manager to join our company Networking team!
As a Formal Verification Manager in our companys Networking Business Unit, you will lead a team of highly skilled formal engineers responsible for verifying the next generation of our companys cutting-edge Network products and GPU technologies.
This is a unique opportunity to make a real impact at the heart of our companys AI and HPC revolution, while working in a fast-paced, innovative environment.
You will be part of a passionate and experienced team using leading formal verification tools and methodologies to ensure design correctness at the highest level. Your work will influence key architectural decisions and help deliver world-class silicon solutions for data centers, high-performance computing, networking, and storage applications.
What Youll Be Doing:
Lead and grow a team of formal verification engineers focused on pre-silicon Formal verification of complex digital designs.
Define and drive formal verification strategies and methodologies to prove the correctness of designs across multiple projects.
Collaborate closely with Architecture, Design, DV teams to identify verification needs and drive closure.
Provide technical guidance, mentoring, and support to engineers in the team.
Own the planning and execution of formal verification deliverables to ensure high quality and timely tapeouts.