Senior VLSI CDC Engineer

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7 ימים

Senior VLSI Integration Engineer

חברה חסויה

Location: More than one

Job Type: Full Time

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
7+ years of actual design experience in chip design
Solid hands-on RTL design skills in System-Verilog
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.
Way to stand out from the crowd:
Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.

This position is open to all candidates.

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3 ימים

Senior CDC Engineer, Chip Design

חברה חסויה

Location: Tel Aviv-Yafo

Job Type: Full Time

our company networking unit is a world-leader fast-growing company which supports the most powerful supercomputers in the world. We make outstanding artificial intelligence happen and accelerate Open-AIs Chat-GPT, for example. We believe in our people and products and seek excellent people to join us!
We are looking for a CDC Design Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
You will play a major role analyzing the design and driving fixes as well as developing, maintaining, and improving our Lint, Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) constraints and methodology for our SOCs across block level, cluster level, and/or full chip level.
Responsibility for analyzing and optimizing the CDC and RDC sign-offs.
Develop and maintain key CDC/RDC checks and associated sign-offs for SOCs.
Help in driving frontend and backend assertions needed to support CDC/RDC constraints and assumptions.
Learn and understand the switch u/architecture to support the design and verification teams.

Requirements:
B.Sc. in Electrical Engineering from a known university.
Excellent grades.
5+ years of experience in ASIC design/uarch/arch/performance.
At least 4 years of hands on experience in writing Verilog/VHDL.
Strong analytic capabilities, and passion for solving logical issues.
Strong debug skills.
Experience in Python, Tcl and Make for automation and scripting tasks.
Ability to drive complex activities involving many interfaces and teams.
Good communication skills.
Ways to stand out from the crowd:
Experience in RTL Design, Synthesis and Timing and as an HW-architect.
Experience with tools like Synopsys PrimeTime, Spyglass, VC-Static, or Meridian.
Knowledge in switching fabrics with strict performance requirements. (Networking, SOC connectivity, etc).
Familiar with working on large high-end ASICs.
Experience in performance improvements in ASICExpertise in Static Timing Analysis (STA), Clock-Domain Crossing (CDC), and Reset Domain Crossing (RDC) solutions.

This position is open to all candidates.

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25/08/2025

SOC Clock Distribution Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company's System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.

Requirements:
B.SC. in Electrical Engineering/Computer Engineering.
3+ years of confirmed experience in chip design
Shown hands on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
Proficiency in at least one common scripting languages like perl, python, bash, Tcl.
Phenomenal teammate.
Ways to stand out from the crowd:
Passion for quality. Experience with delivery back to RTL, to physical design, and other customers.

This position is open to all candidates.

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לפני 14 שעות

SOC Clock Distribution Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top physical design engineer with a curiosity about SOC design optimization, physical integration, chip build and assembly and verification. You should have real passion for methodologies and clock distribution solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and directly contact unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues.

This position is open to all candidates.

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3 ימים

Clock Design Engineer

חברה חסויה

Location: More than one

Job Type: Full Time

our company has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. Its a unique legacy of innovation thats fueled by great technologyand amazing people. Today, were tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing whats never been done before takes vision, innovation, and the worlds best talent. As a worker, youll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
The complexity of the chip has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. The our company System-On-Chip (SOC) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly and verification. You should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way. In this position, you will get the opportunity to build complex networking chips and interact directly with unit-level owners, Physical Design, CAD, Package Design, Software, DFT and other teams.
What you'll be doing:
Designing and implementing SOC level clock requirements
Developing and deploying automation flows which support SOC level design
Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, emulation, resolve design quality issues.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
3+ years of relevant experience in chip design
Solid hands-on RTL design skills in Verilog
Proficiency in at least one common scripting languages like python, bash, tcl.
Great teammate.
Ways to stand out from the crowd:
Passion for quality. Experience with delivery to physical design, emulation, firmware and other customers.

This position is open to all candidates.

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3 ימים

Senior VLSI Integration Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

we are looking for best-in-class Senior VLSI integration Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Implement Chip level design through collaboration with cross-functional teams (Functional Design, DFT, Design Verification, System Verification, STA, and Physical Design) .
Be exposed and work on a variety of functional and structural challenges. Including functional debug, getting ready for physical design, emulation, resolve design quality issues.
Daily work involves aspects of chip level design, including partitioning, CDC, RDC, trial synthesis, design quality checks
Taking part in flows development and deployment.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
10+ years of actual design experience in chip design
Solid hands-on RTL design skills in System-Verilog
Passion for quality and readiness to physical design, emulation, firmware and other customers
Proficiency in at least one scripting languages like python, bash, tcl.
Great teammate.

This position is open to all candidates.

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06/08/2025

Senior VLSI Backend Engineer

חברה חסויה

Location: Yokne`am

Job Type: Full Time

We are looking for talented and ambitious individuals to join our Yoqneam IC team.

Responsibilities:
The candidate will join our BE team, focusing on Full-Chip floor-planning, timing closure and integration, collaborating closely with frontend design, architecture, physical design, and analog teams. Additionally, the candidate will provide support to design teams across various methodologies and contribute to project execution efforts.
What will the candidate be doing
Lead Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
Floor Planning Top to Bottom & Bottom up FC, Sub System & Block level.
Involved in chip architecture, in close collaboration with the packaging, design & architecture teams. Exploring different floorplan structures to achieve both best area & ease of convergence.
Drive sign-off timing convergence for high performance designs at Full-chip and building block level.
Involved in definition of overall STA methodology, STA infrastructure and sign-off convergence flows, working closely with block owners throughout the project for sign-off timing convergence.
Work closely with EDA (Electronic Design Automation) vendors on latest tool feature development and qualification.

Requirements:
Requirements:
BSc or MSc in Electrical Engineering or Computer Engineering.
8+ years experience in full chip design.
Experience in leading the full-chip level design and successfully taping out multiple intricate SoCs.
Experience in floor planning, integration, signoff methodologies, and signoff tools for hierarchical designs.
Experience with SoC design practices such as multiple voltage and clock domains, integration of mixed-signal IPs and I/O integration.
Expert knowledge of the entire backend design flow from RTL to TO.
Experience with STA (Static Timing Analysis) tools like primetime or tempus.
Experience with IR drop tools like Ansys Redhawk or Volta's.
Physical Verification Expert (DRC/LVS).
Strong independent and motivated to learn quickly, hard-working, and is results oriented.
Good social skills and ability to work collaboratively with other teams.

Advantages:
Experience with high-speed serial interfaces such as PCIe, DDR, Ethernet.
Familiarity with advanced DFT flows & tools.
Strong proficiency in scripting language, such as, Perl, Tcl, Python, Make, and automation methods/algorithms.

This position is open to all candidates.

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25/08/2025

Senior ASIC Clock Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

our copmpany's Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of our company Networking chips. We're looking for profound and multi-disciplinary background in Clock design domains to lead Clocks Micro-Architecture activities. This role requires working with multiple teams as Architecture, IP, Physical design, Timing and Post-Si teams. Complexity of clocking scheme has grown substantially over recent chip generations with increased focus on performance, power and quality. Modern Clocking design needs to balance high frequency clocks with power, DFx, noise, circuit and physical design constraints.
What you will be doing:
Working on next generation of Networking Switch, NIC and SoC products.
Micro architect and design next generation clock topologies and modules.
ASIC Clock scheme definition.
Improve Power, Performance, and Area (PPA) of state-of-the-art company chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
Collaborate with Physical design and timing team to evaluate Clocking concerns and come up with solutions for supporting high speed Clocking.
Understand physical aspects of the chip and develop enhanced clock distribution techniques.
Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Support Post-Si debug, characterization and productization activities.

Requirements:
BSc or MSc degrees in EE or equivalent experience from known universities.
At least 5+ years of work experience in RTL design, Gate-Level and Circuit design optimization.
Deep understanding of logic optimization techniques and PPA trade-offs.
Excellent interpersonal skills and ability to collaborate with multiple teams.
Excellent problem solving and debugging skills.
Ways to stand out from the crowd:
Prior experience in RTL design (Verilog), verification and synthesis.
Clock IPs profound knowledge: PLL, DLL, Compensator.
Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a bonus. Prior experience in implementing on-chip clocking networks.

This position is open to all candidates.

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27/08/2025

Senior ASIC Design Engineer

חברה חסויה

Location: Tel Aviv-Yafo and Yokne`am

Job Type: Full Time

we are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.
As a design engineer in the DFT design team at our company, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.

Requirements:
B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.
15+ years of practical experience.
Exposure to rtl implementation and coding.
Familiarity with verification tools.
Strong debugging, problem solving and analytical skills.
Strong communication and social skills are required.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
Ways to stand out from the crowd:
Prior Design or Verification experience.
Experience in developing sophisticated design blocks.
Integration of design elements to large cluster or full-chip.
Experience in working with back-end on area, power and timing closures.
Scripting ability.

This position is open to all candidates.

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2 ימים

Physical Design Signoff CAD Engineer

חברה חסויה

Location: Yokne`am

Job Type: Full Time

we are looking for best-in-class Physical Design CAD Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will be developing physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
Work closely with block owners, full Chip STA engineers to assure high quality and timely convergence.
Come up with unique and creative solutions to the state of the art physical design problems that are needed for Our chips.
Additional responsibilities include participating and developing flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM and back-end verification across multiple projects.

Requirements:
B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
1+ years of experience
Self-motivation, attention to detail, and good written, verbal, and presentation skills are critical to success in this role.
Ownership, self-learning skills, and ability to work autonomously
Ways to stand out from the crowd:
Experience in Signoff domains: STA (PrimeTime), Power Estimation (PrimePower), Power Integrity (RedHawk), Formal eq. (Formality)
Knowledge in Tcl/Perl/Python
Versatile
Great teammate.

This position is open to all candidates.

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