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לפני 13 שעות
Location: Yokne`am
Job Type: Full Time
We are now looking for best-in-class Senior Chip Design Verification Engineer to join our outstanding Network Adapter Silicon group, developing the industry's best high-speed smart communication devices, Data Processing Unit (DPU), delivering the highest throughput and lowest latency! Come and take a significant part in verifying and designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a huge impact in a technology-focused company.
What you'll be doing:
Work within a Networking Fullchip team, which is responsible for delivering the chip to tapeout and serves as a critical verification stage before final chip release.
Gain a strong understanding of chip micro-architecture and features, and develop the verification strategyincluding checkers, testcases, and debug plans - for fullchip/cluster level validation.
Enable and validate new features at the fullchip/cluster level, ensuring high quality and reliability under challenging constraints.
Be an integral part of an innovative team, actively participating in the creation and implementation of new verification infrastructures using advanced AI tools.
Requirements:
B.Sc. or above in Electrical Engineering or Computer Engineering.
5+ years of validated experience.
Professional verification experience, knowledge in advanced verification methodologies and tools.
A team player with excellent communication and interpersonal skills.
Strong debugging, problem solving and analytical skills.
Demonstrates deep understanding in design and verification logic.
Self-motivated, ability to work independently and drive tasks to completion.
Ways to stand out from the crowd:
Prior design or verification experience of high-speed interconnects, smart NIC and/or SoC.
Experience in developing verification environments in Specman and/or prior knowledge in Verilog.
Knowledge in network flows and protocols.
This position is open to all candidates.
 
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לפני 16 שעות
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are looking for a Senior Chip Design Verification Engineer for developing the next generation DFT technologies.
As a Senior Chip Design Verification Engineer in the DFT team at our company, you will verify the design and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and complex products. Our DFT solutions are unique, innovative, and we are continuously looking for new and creative solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for verification of the DFT design, architecture and micro-architecture using sophisticated verification methodologies.
As a member of our DFT verification team, you'll understand the design & implementation, define the verification scope, develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors), execute test/coverage plans, and verify the correctness of the design.
Collaborate with architects, designers, emulation, production testing and silicon verification teams to accomplish your tasks.
Requirements:
BSc. in Electrical Engineering or Computer engineering, or equivalent experience.
5+ years of practical verification experience.
Experience in developing verification environments and random based verification for unit level and system level using verification tools (simulation tools, Verilog, debug tools like Simvision/Debussy).
Experience with Specman is a plus.
Good understanding of RTL design (Verilog).
Strong debugging, problem solving and analytical skills.
Excellent communication and social skills.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
This position is open to all candidates.
 
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לפני 14 שעות
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
we are looking for a Senior Chip-Design Verification Engineer to join our Network Adapter Silicon group. As a Senior Verification Engineer at our company Networking Silicon team, you will join a group of passionate engineers to design and implement the next generation state-of-the-art Networking Silicon chips. In this position, you will make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency!
What you'll be doing:
Work in a combined design and verification team which develops core units within the Networking silicon.
Build reference models, verify and simulate chip blocks/entities according to specifications and performance requirements.
Work closely with multiple teams within organizations such as Architecture, Micro- Architecture, FW and Post-Silicon validation.
Requirements:
B.Sc. in Electrical Engineering or Computer Engineering, or equivalent experience.
8+ years of proven experience in RTL verification.
Background in Specman.
Knowledge of HDL (Verilog/VHDL).
A great teammate with good communication and interpersonal skills.
This position is open to all candidates.
 
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לפני 16 שעות
חברה חסויה
Location: More than one
Job Type: Full Time
we are looking for best-in-class STA Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
STA analysis of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of static timing analysis - constraints, environment, models generation and timing ECO generation for block level and full chip level.
Taking part inflows development.
Requirements:
B.SC. in Electrical Engineering/Computer Engineering.
2-3 years of experience as STA engineer.
Ability to quickly adapt to new technology and go deep into new areas
Strong communication skills
Great teammate.
Drive new solutions based on any issues that arise
Ways to Stand Out From the Crowd:
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
This position is open to all candidates.
 
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לפני 13 שעות
Location: Yokne`am
Job Type: Full Time
We are looking for a Senior Formal Verification Engineer for our company Networking team!
This is an exciting opportunity to join a hardworking Pre-Silicon design and verification team, working on groundbreaking NIC technologies. We deploy state-of-the art formal verification tools and methodologies to prove design correctness. Working in our formal verification team will expose you to a wide range of cutting edge design and technologies. Our NIC team delivers world class CPU interface and offload solutions for HPC, data-center, network, and storage markets. We micro-architect, verify, and deliver the best and most widely used high BW ethernet and IB NICs in the industry. our company has the most sophisticated formal tools and methodologies in the industry, which help us achieve A0 design tapeouts. As part of this team, you'll enjoy a versatile work environment, which is educational, dynamic and ambitious.
What you'll be doing:
In this position you will use formal verification algorithms to formally prove the correctness of complicated logic problems.
You will work on ambitious designs along with our Pre-Silicon team and take part in developing the next generation of our company's core technology.
You will learn state of the art formal methodologies and advance your expertise in communication protocols and hardware implementations.
Requirements:
BSc in Electrical/Computer Engineering or MSc in Mathematics, or equivalent experience.
5+ years of relevant experience.
Excellent analytical, logical reasoning and problem-solving skills.
Strong debugging and analytical skills.
Strong communication and interpersonal skills are required.
Ways to stand out from the crowd:
Formal verification work experience.
Knowledge of digital logic.
This position is open to all candidates.
 
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לפני 16 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
we are looking for best-in-class Physical Design Team lead to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you will be doing:
Leading and mentoring Physical Design-Backend team.
Physical design of blocks/top-level according to specifications under challenging constraints targeting for the best power, area, and performance.
Be exposed and work on a variety of challenging designs (including high cell count and HS blocks). Resolving complex timing and congestion problems.
Daily work involves all aspects of physical design chip development (RTL2GDS) - synthesis, power and clock distribution, place and route, timing closure, power and noise analysis, and physical verification.
Taking part inflows development.
Take part in project definition towards POR, close interaction with other domains such as FE, ARCH.
Requirements:
B.SC./ M.SC. or equivalent experience in Electrical Engineering/Computer Engineering.
2+ years of managerial experience.
6+ overall years of experience in physical design.
Proven experience in RTL2GDS flows and methodologies.
Knowledge in physical design flows and methodologies (PNR, STA, physical verification).
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
Great teammate.
This position is open to all candidates.
 
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לפני 16 שעות
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
We are now looking for a best-in-class Senior Chip Design Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer at our company's GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays semiconductor industry our companys GPU Super-Chip.
What youll be doing:
Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU
Integrations and Full-Chip models
Verification of chip blocks/entities according to specifications under challenging constraints
Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration.
Requirements:
5+ years of experience in RTL design verification.
B.Sc. in Electrical Engineering or Computer Engineering.
A team player with good communication and interpersonal skills.
Ways to stand out from the crowd:
Knowledge in Specman and System-Verilog UVM
Knowledge in Networking.
This position is open to all candidates.
 
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לפני 16 שעות
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
we are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
Responsible for chip floorplan and pins placement
Running, debugging and approve Physical verification flows across multiple projects
Perform physical layout planning and optimization.
Requirements:
B.SC./ M.SC. in Electrical Engineering
At least 5+ years of hands-on layout design experience
Strong background of Physical Design Verification methodology LVS/DRC
Knowledge in physical design flows and methodologies (PNR, STA, physical verification)
Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc..)
Great teammate.
This position is open to all candidates.
 
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לפני 13 שעות
Location: Yokne`am
Job Type: Full Time
We are now looking for a Chip Design Verification Engineer. we are seeking a verification engineer to join the chip design methodologies team. The team is in charge of the verification methodologies, shared code, training, and embracing new technologies. One of our main goals is to make sure that the team works in an efficient manner, and provides high-quality deliveries. This position offers the opportunity to have real impact in a dynamic, technology-focused company.
What you'll be doing:
Develop shared verification code and solutions to be widely used by the chip design team.
Develop groundbreaking methodologies to create a flawless experience for verification engineers to keep the focus on new problems.
Collaborate with the design automation team to provide end-to-end solutions that combine verification, simulation, and automation.
Get in touch with EDA vendors to learn about cutting-edge tools/technology and apply them into our verification process.
Understand the design, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Collaborate with designers, verification specialists to accomplish your tasks.
Develop training sessions.
Requirements:
A Bachelors Degree in Electrical Engineering or Computer Science.
Exposure to design and verification tools.
5+ years of hands-on pre-silicon verification experience.
Strong interpersonal skills and ability & desire to innovate.
Ways to stand out from the crowd:
Experience in Specman / System Verilog UVM.
Understanding simulation tools.
Experience in building test benches, evaluate coverage and debug simulation failures.
This position is open to all candidates.
 
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הגשת מועמדותהגש מועמדות
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לפני 14 שעות
חברה חסויה
Location: Tel Aviv-Yafo and Yokne`am
Job Type: Full Time
'we are looking for an Asic Design Engineer to join the DFT design team and develop the next generation DFT technologies.
As a design engineer in the DFT design team at our company, you will participate in definition and implementation of our DFT technologies in various projects. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting Switches, Nic and SoC product lines. We are working closely with a wide range of aspects - chip design, backend, verification and production testing. We are working on the most advanced technologies and sophisticated products, our DFT solutions are unique, innovative, and we are continuously improving and evolving the solutions to meet the challenging goals.
What you'll be doing:
In this position, you will be responsible for defining, coding and integrating sophisticated DFT components into various projects and using state-of-the-art technologies.
As a member of our DFT design team, you will participate in defining various DFT features and improvements, write micro-architecture documents, code design blocks, integrate them into various projects, bring your design to silicon tape-out and silicon testing and production.
Strong collaboration with architects, other design teams, verification, back-end and production testing to accomplish your tasks.
Requirements:
B.Sc. in Electrical Engineering or Computer engineering or equivalent experience.
1+ years of practical experience.
Exposure to rtl implementation and coding.
Familiarity with verification tools.
Strong debugging, problem solving and analytical skills.
Strong communication and social skills are required.
Ability to work in a geographically diverse team environment.
Self motivated, independent and target oriented.
Ways to stand out from the crowd:
Prior Design or Verification experience.
Experience in developing sophisticated design blocks.
Integration of design elements to large cluster or full-chip.
Experience in working with back-end on area, power and timing closures.
Scripting ability.
This position is open to all candidates.
 
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לפני 14 שעות
חברה חסויה
Location: Yokne`am
Job Type: Full Time
we are looking for best-in-class Physical Design Manager to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
We are looking for a highly experienced and motivated Physical Design Manager to lead a team of 1015 engineers as part of our IP development organization. This is a strategic leadership role requiring both deep technical expertise and strong people management skills.
What you will be doing:
Lead and manage a team of 1015 Physical Design engineers, guiding them through all stages of development.
Oversee four concurrent projects, from planning through execution and delivery, working on high-performance and cutting-edge technologies.
Drive technical excellence in floorplanning, synthesis, place & route, timing closure, and physical verification (LVS/DRC).
Collaborate with cross-functional teams, including front-end design, verification, SoC integration, and packaging.
Mentor team members, promote a culture of continuous improvement, and support professional growth.
Ensure timely delivery of project milestones while maintaining high-quality and performance targets.
Requirements:
B.Sc. in Electrical Engineering or a related field; M.Sc. is an advantage.
Minimum of 7 years of hands-on experience in Physical Design.
At least 3 years of proven managerial experience in leading PD teams.
Solid understanding of tools and methodologies in physical implementation (e.g., Synopsys, Cadence, timing analysis, DRC/LVS).
Strong organizational and multitasking skills; ability to manage complex, parallel development streams.
Excellent communication and interpersonal skills.
Fluent in English both written and verbal.
This position is open to all candidates.
 
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