דרושים » הנדסה » R D Analog and Power Hardware Engineer

We are looking for Analog Layout Engineer
About The Position
We are a fast-growing startup developing cutting-edge hardware infrastructure for blockchain and cloud-privacy applications.
Our team takes products from ASIC definition, planning, and implementation all the way through production and deployment in multi-ASIC operational systems.
With a multidisciplinary team boasting decades of experience in developing and manufacturing high-end ASIC products, we set the highest standards for performance, efficiency, and quality.
Roles and responsibilities:
Layout design of sensitive analog circuits where you will need to bring state-of-the-art solutions.
In close co-operation with the Circuit Designer, review and analyze complex analog schematics for layout implementation.
Ensures layout designs best functionality and quality by performing all relevant checks like parasitic checks, IR drop and Electromigration, noise and DFM.
Perform post-layout iterations to ensure the best results.

In this role, you will be responsible for ensuring that the Systems-on-Chip (SoCs) meet the power, thermal, and performance goals. You will play a critical role in the pre and post-silicon validation phases, collaborating with cross-functional teams to identify, debug, and optimize SoC behavior in use cases, as well as validating the IPs protection mechanism.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities
Contribute to developing and improving post-silicon test content that exercises both IP and SoC levels workloads and other compute-intensive scenarios.
Collaborate with architecture, design, and firmware teams to define comprehensive validation plans for SoC features, focusing on power consumption, thermal management, sensors behavior, and performance metrics.
Work with design and firmware teams to propose and implement solutions for optimizing SoC power efficiency and performance, including tuning core-to-memory latencies and bandwidth, power control loops, thermal control loops, etc.
Develop and maintain automated test scripts and frameworks (e.g., Python) to improve validation efficiency and coverage.
Participate in early silicon bring-up and platform bring-up activities, ensuring the stability and functionality of high-power multi-core SoCs.

In this role, you will help to develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our Application-specific integrated circuit (ASIC) projects. You will provide emulation infrastructure and methodologies for supporting these projects. You will work with other emulation team members as well as designers, verification engineers, and software teams. You will work with with our external vendors, lab support teams, networking and security, and Electronic Design Automation (EDA) tooling and methodology teams to deliver emulation based prototyping capabilities for our ASIC projects. You will also assist in compiling projects specifying our prototyping platforms, debugging issues in both infrastructure and design, assisting in the hardware and lab bring up, and verification of our ASIC systems.

Responsibilities
Help in maintaining and upgrading emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in Google infrastructure.
Support emulation team members with debugging hardware, tooling, and project specific issues.
Help to bring up external interfaces (e.g., USB, PCIe, Ethernet, etc.) on the emulation platforms, and create standalone test cases for tool issues encountered in the emulation compile and runtime flows.

We are looking for a Electronics Board Design Engineer.
About The Position:
Development of Electronics Boards/Sub Systems for new technology projects
Development and integration of multi-disciplinary systems which includes HW/SW/Mechanics
Supporting Legacy Electronics & systems
Working according to Quality Policy, relevant Quality Procedures & Standards, and privacy & safety rules.

We are looking for an experienced Hardware Team Lead to manage our Board Design Engineering team within the AV department.
In this critical role, you will drive the development of cutting-edge automotive products by owning the design and delivery of high-performance electronic boards and systems. Your leadership will ensure projects meet the highest standards of quality, performance, and innovation.
What will your job look like?
Lead and Do: Combine strong technical leadership with hands-on hardware engineeringthis role is both strategic and actively involved in execution.
Team Management: Mentor, guide, and grow a high-performing team of hardware engineers, while setting clear technical direction and expectations.
End-to-End Project Ownership: Drive the entire hardware development lifecyclefrom architecture and schematic design to validation and release to mass production.
Design Leadership: Personally contribute and oversee electrical design, schematic reviews, component selection, and layout best practices.
Lab Engagement: Stay closely involved in board bring-up, debugging, and validationworking side by side with engineers to solve tough technical challenges.
Cross-Team Collaboration: Act as a key point of contact across software, mechanical, architecture, and manufacturing teams to ensure seamless product integration.
Customer-Facing Leadership: Represent the hardware team in technical discussions with customers, demonstrating both leadership and in-depth technical knowledge.

we are looking for a Hardware Emulation Engineer, Google Cloud
Responsibilities
Help to maintain and upgrade emulation infrastructure and act as a primary interface to emulation vendors.
Explore emulation methodologies, gather feedback from the team, and implement emulation workflows and methodologies.
Create tooling and automation to support emulation Electronic Design Automation (EDA) tools, licensing, and job management in infrastructure.
Support emulation team members in debugging hardware, tooling, and project specific issues.
Help bring up external interfaces (e.g., USB, Peripheral Component Interconnect Express (PCIe), Ethernet, etc.) on the emulation platforms, and create test cases for tool issues encountered in the emulation compile and runtime flows.

Required Physical Design Engineer
About The Position:
We design and builds hardware that fuels disruptive blockchain technologies by accelerating compute performance. Our world-class teams are transforming the future of data, creating the infrastructure that will power the next generation of secure, scalable, green computing. The main bottleneck in scaling cutting-edge solutions in privacy tech, data analysis, and real-time computing is acceleration existing hardware cannot keep up with data processing needs. Our products reshape how data is processed and used on a global scale, and were looking for the brightest people to join us. We are seeking talented and driven individuals to become part of our Yoqneam IC team.
Responsibilities:
Floor Planning Top to Bottom & Bottom up Block level. Exploring different floorplan structures to achieve both the best area & ease of convergence.
Generate high-quality PnR results for one or more digital blocks by applying engineering best practices.
Optimize designs based on key metrics, including power, area, and performance trade-off analyses.
Drive sign-off timing convergence for high-performance designs at the block level, including DRC and LVS signoff
Analyze power integrity (EMIR) results of blocks and apply corrective measures to resolve identified issues.
Collaborating closely with frontend, verification, architecture, physical design, and analog teams.
Work closely with EDA (Electronic Design Automation) vendors on the latest tool feature development and qualification.